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description the 3826 group (a version) is the 8-bit microcomputer based on the 740 family core technology. the 3826 group (a version) has the lcd drive control circuit, an 8- channel a-d converter, d-a converter, serial i/o and pwm as ad- ditional functions. the various microcomputers in the 3826 group (a version) include variations of internal memory size and packaging. for details, re- fer to the section on part numbering. for details on availability of microcomputers in the 3826 group (a version), refer the section on group expansion. features ? basic machine-language instructions ....................................... 71 ? the minimum instruction execution time ............................ 0.4 s (at 10 mhz oscillation frequency) ? memory size rom ................................................................ 48 k to 60 k bytes ram ............................................................... 1536 to 2560 bytes ? programmable input/output ports ............................................. 55 ? software pull-up resistors .................................................... built-in ? output ports ................................................................................. 8 ? input ports .................................................................................... 1 ? interrupts .................................................. 17 sources, 16 vectors external ................ 7 sources (includes key input interrupt) internal ................................................................ 9 sources software ................................................................ 1 source ? t imers ............................................................ 8-bit ? 3, 16-bit ? 2 ? serial i/o1 ..................... 8-bit ? 1 (uart or clock-synchronous) ? serial i/o2 .................................... 8-bit ? 1 (clock-synchronous) ? pwm output .................................................................... 8-bit ? 1 ? a-d converter .................................................. 8-bit ? 8 channels ? d-a converter .................................................. 8-bit ? 2 channels (used as dtmf and ctcss function) ? lcd drive control circuit bias ......................................................................... 1/2, 1/3 duty .................................................................. 1/2, 1/3, 1/4 common output ................................................................ 4 segment output .............................................................. 40 ? 2 clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) ? w atchdog timer ............................................................. 14-bit ? 1 ? power source voltage in high-speed mode (f(x in ) = 10 mhz) ................... 4.5 v to 5.5 v in high-speed mode (f(x in ) = 8 mhz) ..................... 4.0 v to 5.5 v in middle-speed mode (f(x in ) = 6 mhz) ................. 1.8 v to 5.5 v in low-speed mode .................................................. 1.8 v to 5.5 v ? power dissipation in high-speed mode ................................................... t yp. 28 mw (at 10mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ...................................................... t yp. 27 w (at 32khz oscillation frequency, at 3 v power source voltage) ? operating temperature range ................................... ? 20 to 85c applications camera, cordless phone, wireless application, etc. 3826 group (a version) single-chip 8-bit cmos microcomputer rej03b0029-0101z rev.1.01 2003.08.22 rev.1.01 aug 22, 2003 page 1 of 69
rev.1.01 aug 22, 2003 page 2 of 69 3826 group (a version) package type : 100p6q-a pin configuration (top view) fig. 2 pin configuration (package type: 100p6q-a) package type : 100p6s-a fig. 1 pin configuration (package type: 100p6s-a) pin configuration (top view) 12345 678910111 2131415161718192021222324252627282930 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 m3826xmxa-xxxfp seg 9 p3 1 /seg 19 p3 0 /seg 18 p3 2 /seg 20 p3 3 /seg 21 p3 4 /seg 22 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 p3 5 /seg 23 p3 6 /seg 24 p3 7 /seg 25 p0 0 /seg 26 p0 1 /seg 27 p0 2 /seg 28 p0 3 /seg 29 p0 4 /seg 30 p0 5 /seg 31 p0 6 /seg 32 p0 7 /seg 33 p1 0 /seg 34 p1 1 /seg 35 p1 2 /seg 36 p1 3 /seg 37 p1 4 /seg 38 p1 5 /seg 39 c 1 v l1 p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 2 /s clk21 /an 2 p6 1 /s out2 /an 1 p6 0 /s in2 /an 0 p5 7 /adt/da 2 p5 6 /da 1 p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /rtp 1 p5 2 /rtp 0 p5 1 /pwm 1 p5 0 /pwm 0 p4 6 /s clk1 p4 5 /t x d p4 4 /r x d p4 3 / /t out p4 2 /int 2 p4 1 /int 1 p4 0 p7 7 p7 6 p7 5 p7 4 c 2 v l2 v l3 com 0 com 1 com 2 v ref av ss v c c seg 8 seg 0 seg 1 seg 2 seg 4 seg 5 seg 6 seg 7 seg 3 p7 2 p7 3 p7 1 p7 0 /int 0 x cin x cout x in x out v ss p2 7 p2 6 p2 5 p2 4 p2 3 p2 1 p1 6 p2 2 p2 0 p1 7 reset seg 16 seg 17 com 3 p4 7 /s rdy1 p6 3 /s clk22 /an 3 1234567891011121314151 6171819202122232425 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 1 m3826xmxa-xxxgp seg 12 seg 11 seg 10 seg 9 seg 8 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 seg 1 seg 0 v cc v ref av ss com 3 com 2 com 1 com 0 v l3 v l2 c 2 c 1 v l1 p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p5 7 /adt/da 2 p5 6 /da 1 p5 5 /cntr 1 p5 4 /cntr 0 p4 1 /int 1 p4 0 p4 3 / /t out p5 3 /rtp 1 p5 2 /rtp 0 p5 1 /pwm 1 p5 0 /pwm 0 p7 7 p4 2 /int 2 p7 2 p7 3 p7 1 p7 0 /int 0 x cin x cout x in x ou t v ss p2 7 p2 6 p2 5 p2 4 p2 3 p2 1 p1 6 p2 2 p2 0 p1 7 reset p7 6 p7 5 p7 4 p1 5 /seg 39 p1 4 /seg 38 p3 1 /seg 19 p3 0 /seg 18 p3 2 /seg 20 p3 3 /seg 21 p3 4 /seg 22 seg 13 seg 14 seg 15 p3 5 /seg 23 p3 6 /seg 24 p3 7 /seg 25 p0 0 /seg 26 p0 1 /seg 27 p0 2 /seg 28 p0 3 /seg 29 p0 4 /seg 30 p0 5 /seg 31 p0 6 /seg 32 p0 7 /seg 33 p1 0 /seg 34 p1 1 /seg 35 p1 2 /seg 36 p1 3 /seg 37 seg 16 seg 17 p6 2 /s clk21 /an 2 p6 1 /s out2 /an 1 p6 0 /s in2 /an 0 p6 3 /s clk22 /an 3 p4 6 /s clk1 p4 5 /t x d p4 4 /r x d p4 7 /s rdy1
rev.1.01 aug 22, 2003 page 3 of 69 3826 group (a version) functional block diagram (package type: 100p6s-a) fig. 3 functional block diagram int 1, int 2 cntr 0 ,cntr 1 da 1 adt c p u a x y s pc h pc l ps reset v cc v ss ( 5 v ) ( 0 v ) r o m r a m 35 91 40 p4(8) p2(8) p0(8) p1(8) p6(8) p7(8) p3(8) p5(8) 1 2 100 99 98 97 96 95 94 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 57 58 59 60 61 62 63 64 49 50 51 52 53 54 55 56 41 42 43 44 45 46 47 48 65 66 67 68 69 70 71 72 19 20 21 22 23 24 25 26 36 37 27 28 29 30 31 32 33 34 345 678 910 93 92 11 12 13 14 15 16 17 18 x cin x cout x in out x cout x x cin si/o1 (8) v ref av ss v l1 c 1 c 2 v l2 v l3 com 0 com 1 com 2 com 3 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 x cin cout x 38 39 si/o2(8) pwm(8) int 0 d-a2/ctss d-a1/dtmf da 2 t out lcd drive control circuit lcd display ram (20 bytes) timer x (16) timer y (16) timer 1 (8) timer 2 (8) timer 3 (8) data bus clock generating circuit main clock input main clock output sub-clock output sub-clock input reset key input (key-on wake up) interrupt real time port function a-d converter (8) i/o port p0 i/o port p1 i/o port p2 i/o port p4 i/o port p5 i/o port p6 output port p3 i/o port p7 reset input sub- clock output sub- clock input watchdog timer
rev.1.01 aug 22, 2003 page 4 of 69 3826 group (a version) pin description t able 1 pin description (1) v cc v ss function pin name function except a port function ? lcd segment output pins power source ? apply voltage of power source to v cc , and 0 v to v ss . (for the limits of v cc , refer to ?recom- mended operating conditions?. v ref av ss reset x in x out v l1 ?v l3 c 1 , c 2 com 0 ?com 3 seg 0 ?seg 17 p0 0 /seg 26 ? p0 7 /seg 33 p1 0 /seg 34 ? p1 5 /seg 39 p1 6 , p1 7 p2 0 ? p2 7 p3 0 /seg 18 ? p3 7 /seg 25 analog refer- ence voltage analog power source reset input clock input clock output lcd power source charge-pump capacitor pin common output segment output i/o port p0 i/o port p1 i/o port p2 output port p3 ? reference voltage input pin for a-d converter and d-a converter. ? gnd input pin for a-d converter and d-a converter. ? connect to v ss . ? reset input pin for active ?l?. ? input and output pins for the main clock generating circuit. ? connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ? if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. a feedback resistor is built-in. ? input 0 v l1 v l2 v l3 voltage. ? input 0 ? v l3 voltage to lcd. (0 v l1 v l2 v l3 when a voltage is multiplied.) ? external capacitor pins for a voltage multiplier (3 times) of lcd control. ? lcd common output pins. ? com 2 and com 3 are not used at 1/2 duty ratio. ? com 3 is not used at 1/3 duty ratio. ? lcd segment output pins. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? pull-up control is enabled. ? i/o direction register allows each 8-bit pin to be pro- grammed as either input or output. ? 6-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? pull-up control is enabled. ? i/o direction register allows each 6-bit pin to be pro- grammed as either input or output. ? 2-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 8-bit output. ? cmos 3-state output structure. ? port output control is enabled. ?key input (key-on wake-up) interrupt input pins ?lcd segment output pins
rev.1.01 aug 22, 2003 page 5 of 69 3826 group (a version) t able 2 pin description (2) function pin name function except a port function p4 0 p4 1 /int 1 , p4 2 /int 2 p4 3 / /t out p4 4 /r x d, p4 5 /t x d, p4 6 /s clk1 , p4 7 /s rdy1 p5 0 /pwm 0 , p5 1 /pwm 1 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 , p5 5 /cntr 1 p5 6 /da 1 p5 7 /adt/da 2 p6 0 /s in2 /an 0, p6 1 /s out2 /an 1, p6 2 /s clk21 /an 2, p6 3 /s clk22 /an 3 p6 4 /an 4 ? p6 7 /an 7 p7 0 /int 0 p7 1 ?p7 7 i/o port p4 i/o port p5 i/o port p6 input port p7 i/o port p7 sub-clock output sub-clock input ? 1-bit i/o port. ? cmos compatible input level. ? n-channel open-drain output structure. ?i/o direction register allows this pin to be individually programmed as either input or output. ? 7-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ?i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ?i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ?8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ?i/o direction register allows each pin to be individually programmed as either input or output. ? pull-up control is enabled. ? 1-bit input port. ?int i interrupt input pins ?system clock output pin ?timer 2 output pin ?serial i/o1 i/o pins ?pwm output pins ?real time port output pins ?timer x, y i/o pins ?d-a converter output pin ?d-a converter output pin ?a-d external trigger input pin ?a-d converter input pins ?serial i/o2 i/o pins ?a-d converter input pins x cout x cin ?int 0 interrupt input pin ? 7-bit i/o port. ? cmos compatible input level. ? n-channel open-drain output structure. ?i/o direction register allows each pin to be individually programmed as either input or output. ? sub-clock generating circuit i/o pins. (connect a oscillator. external clock cannot be used.)
rev.1.01 aug 22, 2003 page 6 of 69 3826 group (a version) p art numbering fig. 4 part numbering m3826 m f a ? xxx fp product rom size 1 2 3 4 5 6 7 8 9 a b c d e f : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. memory type m: mask rom version rom number package type fp gp : 100p6s-a : 100p6q-a characteristics a : a version
rev.1.01 aug 22, 2003 page 7 of 69 3826 group (a version) group expansion renesas expands the 3826 group (a version) as follows. memory type support for mask rom version. memory size rom size ........................................................... 48 k to 60 k bytes ram size .......................................................... 1536 to 2560 bytes packages 100p6q-a .................................. 0.5 mm-pitch plastic molded qfp 100p6s-a ................................ 0.65 mm-pitch plastic molded qfp memory expansion plan fig. 5 memory expansion plan t able 3 support products as of jul. 2003 remarks mask rom version mask rom version mask rom version mask rom version package 100p6s-a 100p6q-a 100p6s-a 100p6q-a part number m38268m8a-xxxfp m38268m8a-xxxgp m3826amfa-xxxfp m3826amfa-xxxgp ram size (bytes) 1536 49152 (49022) 61440 (61310) rom size (bytes) rom size for user in ( ) 2560 rom size (bytes) ram size (bytes) 256 512 768 1024 1280 1536 1792 192 2048 2304 2560 32k 28k 24k 20k 16k 12k 8k 4k 52k 48k 44k 40k 36k 56k 60k m38268mca m3826amfa
rev.1.01 aug 22, 2003 page 8 of 69 3826 group (a version) functional description central processing unit (cpu) the 3826 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instruction cannot be used. the stp, wit, mul, and div instruction can be used. the central processing unit (cpu) has six registers. figure 6 shows the 740 family cpu register structure. [accumulator (a)] the accumulator is an 8-bit register. data operations such as arithmetic data transfer, etc., are executed mainly through the ac- cumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack address are determined by the stack page selection bit. if the stack page selection bit is ?0? , the high-order 8 bits becomes ?00 16 ?. if the stack page selection bit is ?1?, the high-order 8 bits becomes ?01 16 ?. figure 9 shows the operations of pushing register contents onto the stack and popping them from the stack. table 6 shows the push and pop instructions of accumulator or processor status reg- ister. store registers other than those described in figure 9 with pro- gram when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h a nd pc l . it is used to indicate the address of the next instruction to be executed. fig. 6 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h nv tb di zc processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
rev.1.01 aug 22, 2003 page 9 of 69 3826 group (a version) t able 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 7 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t r e q u e s t h e r e e x e c u t e j s r on-going routin e m ( s )( p c h ) ( s ) ( s ) ? 1 m ( s )( p c l ) e x e c u t e r t s (pc l )m (s) ( s ) ( s ) ? 1 ( s ) ( s ) + 1 (s) (s) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m (s )( ps) exec ute rti ( p s )m ( s ) (s) (s) ? 1 (s) (s) + 1 i n t e r r u p t s e r v i c e r o u t i n e pop c ontents of processor status register from stack m ( s )( p c h ) (s) (s) ? 1 m ( s )( p c l ) (s) (s) ? 1 (pc l )m (s) (s) (s) + 1 (s) (s) + 1 (pc h )m (s) pop re turn address from stack i f l a g i s s e t f r o m ? 0 ? t o ? 1 ? f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k push contents of processor status register on stack interr upt request (note) interrupt enable bit corresponding to each interrupt source is ?1? interrupt disable flag is ?0?
rev.1.01 aug 22, 2003 page 10 of 69 3826 group (a version) [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. ? bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arith- metic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. ? bit 1: zero flag (z) the z flag is set to ?1? if the result of an immediate arithmetic op- eration or a data transfer is ?0?, and set to ?0? if the result is anything other than ?0?. ? bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt gener- ated by the brk instruction. interrupts are disabled when the i flag is ?1?. ? bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is ?0?; decimal arithmetic is executed when it is ?1?. decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. ? bit 4: break flag (b) the b flag is used to indicate that the current interrupt was gen- erated by the brk instruction. when the brk instruction is generated, the b flag is set to ?1? automatically. when the other interrupts are generated, the b flag is set to ?0?, and the proces- sor status register is pushed onto the stack. ? bit 5: index x mode flag (t) when the t flag is ?0?, arithmetic operations are performed be- tween accumulator and memory. when the t flag is ?1?, direct arithmetic operations and direct data transfers are enabled be- tween memory locations. ? bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set to ?1? if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory loca- tion operated on by the bit instruction is stored in the v flag. ? bit 7: negative flag (n) the n flag is set to ?1? if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. t able 5 instructions to set each bit of processor status register to ?0? or ?1? instruction setting to ?1? instruction setting to ?0? c flag sec clc z flag ? ? i flag sei cli d flag sed cld b flag ? ? t flag set clt v flag ? clv n flag ? ?
rev.1.01 aug 22, 2003 page 11 of 69 3826 group (a version) [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the system clock control bits, etc. the cpu mode register is allocated at address 003b 16 . fig. 8 structure of cpu mode register p rocessor mo d e bi ts b1 b0 0 0 : single-chip mode 0 1 : 1 0 : 1 1 : stack page selection bit 0 : 0 page 1 : 1 page not used (?1? at reading) (write ?1? to this bit at writ ing) x c switch bit 0 : o scillation stop 1 : x cin ?x cout oscillati ng function main cl o ck (x in ? x out ) st op bit 0 : o scillating 1 : stopped main clo ck division ratio selection bit 0 : f(x in )/2 (high-speed mode) 1 : f(x in )/8 (middle-speed mode) s ystem clock selection bit 0 : x in ?x out selected (middle -/hi gh-speed mode) 1 : x cin ?x cout selected (low -s peed mode) d o not se l ect cp u mode register ( c p u m ( c m ) : a d d r e s s 0 0 3 b 1 6 ) b 7 b 0 1
rev.1.01 aug 22, 2003 page 12 of 69 3826 group (a version) memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 9 memory map diagram 1 9 2 2 5 6 3 8 4 5 1 2 6 4 0 7 6 8 8 9 6 1 0 2 4 1 5 3 6 2 0 4 8 2 5 6 0 00 ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 0a3f 16 r a m a r e a r a m s i z e ( b y t e s ) a d d r e s s x x x x 1 6 4 0 9 6 8 1 9 2 1 2 2 8 8 1 6 3 8 4 2 0 4 8 0 2 4 5 7 6 2 8 6 7 2 3 2 7 6 8 3 6 8 6 4 4 0 9 6 0 4 5 0 5 6 4 9 1 5 2 5 3 2 4 8 5 7 3 4 4 6 1 4 4 0 f 0 0 0 1 6 e 0 0 0 1 6 d 0 0 0 1 6 c 0 0 0 1 6 b 0 0 0 1 6 a 0 0 0 1 6 9 0 0 0 1 6 8 0 0 0 1 6 7 0 0 0 1 6 6 0 0 0 1 6 5 0 0 0 1 6 4 0 0 0 1 6 3 0 0 0 1 6 2 0 0 0 1 6 1 0 0 0 1 6 f 0 8 0 1 6 e 0 8 0 1 6 d 0 8 0 1 6 c 0 8 0 1 6 b 0 8 0 1 6 a 0 8 0 1 6 9 0 8 0 1 6 8 0 8 0 1 6 7 0 8 0 1 6 6 0 8 0 1 6 5 0 8 0 1 6 4 0 8 0 1 6 3 0 8 0 1 6 2 0 8 0 1 6 1 0 8 0 1 6 rom area rom s i ze (byt es) a d d r e s s y y y y 1 6 a d d r e s s z z z z 1 6 0100 16 0000 16 0040 16 ff 00 16 ffdc 16 f f f e 1 6 ffff 16 xxxx 16 yyyy 16 zzzz 16 ram r o m 0054 16 s f r a r e a n o t u s e d i n t e r r u p t v e c t o r a r e a r eserve d rom area (128 bytes) z e r o p a g e s p e c i a l p a g e lcd di sp l ay ram area r e s e r v e d r o m a r e a
rev.1.01 aug 22, 2003 page 13 of 69 3826 group (a version) fig. 10 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 register (p0) port p1 register (p1) port p1 direction register (p1d) port p2 register (p2) port p2 direction register (p2d) port p3 register (p3) port p4 register (p4) port p4 direction register (p4d) port p5 register (p5) port p5 direction register (p5d) port p6 register (p6) port p6 direction register (p6d) port p7 register (p7) port p7 direction register (p7d) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) interrupt control register 2(icon2) timer 3 register (t3) timer x mode register (txm) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1(ireq1) interrupt request register 2(ireq2) interrupt control register 1(icon1) timer x low-order register (txl) timer y low-order register (tyl) timer 1 register (t1) timer 2 register (t2) timer x high-order register (txh) timer y high-order register (tyh) pull register a (pulla) pull register b (pullb) timer y mode register (tym) timer 123 mode register (t123m) t out / output control register (ckout) segment output enable register (seg) lcd mode register (lm) a-d control register (adcon) a-d conversion register (ad) transmit/receive buffer register (tb/rb) key input control register (kic) port p0 direction register (p0d) port p3 output control register (p3c) reserved area (note) serial i/o2 control register (sio2con) serial i/o2 register (sio2) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) ctscss timer (low) (ctcssl) ctscss timer (high) (ctcssh) dtmf high group timer (dtmfh) dtmf low group timer (dtmfl) d-a1 conversion register (da1) d-a2 conversion register (da2) d-a control register (dacon) watchdog timer control register (wdtcon) note: do not write to the addresses of reserved area. reserved area (note)
rev.1.01 aug 22, 2003 page 14 of 69 3826 group (a version) i/o ports direction registers the i/o ports (ports p0, p1, p2, p4, p5, p6, p7 1 ?p7 7 ) have direc- tion registers. ports p1 6 , p1 7 , p4, p5, p6, and p7 1 ?p7 7 can be set to input mode or output mode by each pin individually. p0 0 ?p0 7 and p1 0 -p1 5 are respectively set to input mode or output mode in a lump by bit 0 of the direction registers of ports p0 and p1 (see figure 11). when ?0? is set to the bit corresponding to a pin, that pin becomes an input mode. when ?1? is set to that bit, that pin becomes an output mode. if data is read from a port set to output mode, the value of the port latch is read, not the value of the pin itself. a port set to input mode is floating. if data is read from a port set to input mode, the value of the pin itself is read. if a pin set to input mode is written to, only the port latch is written to and the pin remains floating. port p3 output control register bit 0 of the port p3 output control register (address 0007 16 ) en- ables control of the output of ports p3 0 ?p3 7 . when the bit is set to ?1?, the port output function is valid. when resetting, bit 0 of the port p3 output control register is set to ?0? (the port output function is invalid) and pulled up. fig. 11 structure of port p0 direction register, port p1 direc- tion register fig. 12 structure of port p3 output control register p o r t s p 0 0 t o p 0 7 d i r e c t i o n r e g i s t e r 0 : i n p u t m o d e 1 : o u t p u t m o d e n o t u s e d ( u n d e f i n e d a t r e a d i n g ) ( i f w r i t i n g t o t h e s e b i t s , w r i t e ? 0 ? . ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d : a d d r e s s 0 0 0 1 1 6 ) b 7 b 0 n ote: i n ports set to output mo d e, t h e pu ll -up co ntro l bi t b ecomes invalid and pull- up resi stor is not co nnected. p o r t s p 1 0 t o p 1 5 d i r e c t i o n r e g i s t e r 0 : i n p u t m o d e 1 : o u t p u t m o d e n o t u s e d ( u n d e f i n e d a t r e a d i n g ) ( i f w r i t i n g t o t h e s e b i t s , w r i t e ? 0 ? . ) p o r t p 1 6 d i r e c t i o n r e g i s t e r p o r t p 1 7 d i r e c t i o n r e g i s t e r 0 : i n p u t m o d e 1 : o u t p u t m o d e p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d : a d d r e s s 0 0 0 3 1 6 ) b 7 b 0 p orts p 3 0 to p 3 7 output contro l bi t 0 : output function is invalid (pulled up) 1 : output function is valid (no pull up) not used (u ndefined at reading) (if writing to these bits, writ e ?0 ?.) p ort p 3 output contro l reg i ster (p3c : address 0007 16 ) b 7 b 0 n ote: i n p i ns se t to segment output b y segment output ena bl e bi ts 0, 1 (bits 0, 1 of segment output enable register (address 38 16 )), this bit becomes invalid and pull-up resistor is not conn ected.
rev.1.01 aug 22, 2003 page 15 of 69 3826 group (a version) fig. 13 structure of pull register a and pull register b pull-up control by setting the pull register a (address 0016 16 ) or the pull reg- ister b (address 0017 16 ), ports p0 to p2, p4 to p6 can control pull-up with a program. however, the contents of pull register a and pull register b do not affect ports set to output mode and the ports are no pulled up. the pull register a setting is invalid for pins selecting segment output with the segment output enable register and the pins are not pulled up. p 0 0 , p 0 1 pu ll -up contro l bi t p0 2 , p0 3 pull-up control bit p0 4 ?p0 7 pull-up control bit p1 0 ?p1 3 pull-up control bit p1 4 , p1 5 pull-up control bit p1 6 , p1 7 pull-up control bit p2 0 ?p2 3 pull-up control bit p2 4 ?p2 7 pull-up control bit p u l l r e g i s t e r a ( p u l l a : a d d r e s s 0 0 1 6 1 6 ) b 7 b 0 p 4 1 ? p 4 3 pu ll -up co ntro l bi t p4 4 ?p4 7 pull-up control bit p5 0 ?p5 3 pull-up control bit p5 4 ?p5 7 pull-up control bit p6 0 ?p6 3 pull-up control bit p6 4 ?p6 7 pull-up control bit not used ?0? at reading) 0 : d i s a b l e 1 : e n a b l e p u l l r e g i s t e r b ( p u l l b : a d d r e s s 0 0 1 7 1 6 ) b 7 b 0 n ote: th e contents o f pull reg i ster a an d pull reg i ster b do no t affect ports set to output mode.
rev.1.01 aug 22, 2003 page 16 of 69 3826 group (a version) pwm output da 2 output ctcss output a-d external trigger input da 1 output dtmf input diagram no. related sfrs input/output name pin non-port function i/o format t able 6 list of i/o port function (1) p0 0 /seg 26 ? p0 7 /seg 33 p1 0 /seg 34 ? p1 5 /seg 39 p1 6 , p1 7 p2 0 ?p2 7 p3 0 /seg 18 ? p3 7 /seg 25 p4 0 p4 1 /int 1 , p4 2 /int 2 p4 3 / /t out p4 4 /r x d, p4 5 /t x d, p4 6 /s clk1 , p4 7 /s rdy1 p5 0 /pwm 0 , p5 1 /pwm 1 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /da 1 p5 7 /adt/ da 2 port p0 port p1 port p2 port p3 port p4 port p5 input/output, byte unit input/output, 6-bit unit input/output, individual bits input/output, individual bits output input/output, individual bits input/output, individual bits cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos 3-state output cmos compatible input level n-channel open-drain output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output lcd segment output lcd segment output key input (key-on wake- up) interrupt input lcd segment output int i interrupt input t imer 2 output system clock output serial i/o1 i/o real time port output t imer x i/o t imer y input pull register a segment output enable register pull register a segment output enable register pull register a pull register a interrupt control register 2 key input control register segment output enable register interrupt edge selection register pull register b t imer 123 mode register t out / output control register pull register b serial i/o1 control register serial i/o1 status register uart control register pull register b pwm control register pull register b t imer x mode register pull register b t imer x mode register pull register b t imer y mode register pull register b d-a control register pull register b d-a control register a-d control register (1) (2) (1) (2) (4) (3) (13) (4) (12) (5) (6) (7) (8) (10) (9) (11) (14) (15) (15) port p3 output control register
rev.1.01 aug 22, 2003 page 17 of 69 3826 group (a version) pin name i/o format non-port function related sfr s diagram no. input/output notes 1: how to use double-function ports as function i/o pins, refer to the applicable sections. 2: make sure that the input level at each pin is either 0 v or v cc before execution of the stp instruction. when an electric potential is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate and power source current may increase. t able 7 list of i/o port function (2) p6 0 /s in2 /an 0 p6 1 /s out2 / an 1 p6 2 /s clk21 / an 2 p6 3 /s clk22 / an 3 p6 4 /an 4 ? p6 7 /an 7 p7 0 /int 0 p7 1 ?p7 7 com 0 ?com 3 seg 0 ?seg 17 port p6 port p7 common segment input/ output, individual bits input input/ output, individual bits output output cmos compatible input level cmos 3-state output cmos compatible input level cmos compatible input level n-channel open-drain output lcd common output lcd segment output a-d converter input serial i/o2 i/o a-d converter input int 0 interrupt input pull register b a-d control register serial i/o2 control register a-d control register pull register b interrupt edge selection register (17) (18) (19) (20) (16) (23) (13) (21) (22) lcd mode register
rev.1.01 aug 22, 2003 page 18 of 69 3826 group (a version) fig. 14 port block diagram (1) (5) port p4 4 (4) ports p1 6 , p1 7 , p2, p4 1 , p4 2 pull-up control v l1 /v ss v l2 /v l3 /v cc v l1 /v ss v l2 /v l3 /v cc v l1 /v ss v l2 /v l3 /v cc (1) ports p0 1 ?p0 7 , p1 1 ?p1 5 data bus port latch interface logic level shift circuit pull-up port segment segment/port lcd drive timing segment output enable bit segment data port direction register port direction register (2) ports p0 0 , p1 0 data bus port latch interface logic level shift circuit port segment segment/port lcd drive timing segment data port direction register direction register pull-up data bus port latch interface logic level shift circuit port segment segment/port lcd drive timing segment data port p3 output control bit pull-up (3) port p3 data bus port latch direction register key input interrupt input int 1 , int 2 interrupt input except p1 6 , p1 7 pull-up control data bus port latch direction register serial i/o1 enable bit serial i/o1 input receive enable bit segment output enable bit segment output enable bit port p3 output control bit
rev.1.01 aug 22, 2003 page 19 of 69 3826 group (a version) fig. 15 port block diagram (2) (6) port p4 5 (7) port p4 6 (8) port p4 7 (9) ports p5 2 ,p5 3 (10) ports p5 0 ,p5 1 pwm function enable bit pwm output (11) port p5 4 pulse output mode timer output cntr 0 interrupt input pull-up control direction register data bus port latch serial i/o1 output p4 5 /txd p-channel output disable bit serial i/o1 enable bit transmit enable bit serial i/o1 clock output direction register data bus port latch pull-up control serial i/o1 enable bit serial i/o1 clock input serial i/o1 synchronous clock selection bit serial i/o1 mode selection bit serial i/o1 enable bit pull-up control serial i/o1 mode selection bit serial i/o1 enable bit s rdy1 output enable bit direction register data bus port latch serial i/o1 ready output direction register data bus port latch pull-up control real time port control bit real time port data pull-up control direction register data bus port latch pull-up control direction register data bus port latch
rev.1.01 aug 22, 2003 page 20 of 69 3826 group (a version) fig. 16 port block diagram (3) (12) port p4 3 t out / output enable bit timer 2 t out output system clock output t out / output selection bit (13) ports p4 0 ,p7 1 ?p7 7 (14) port p5 5 cntr 1 interrupt input (15) ports p5 6 ,p5 7 a-d external trigger input d-a converter output except p5 6 (16) ports p6 4 ?p6 7 (17) port p6 0 analog input pin selection bit a-d converter input serial i/o2 input da 1 , da 2 output enable bits direction register port latch data bus pull-up control direction register port latch data bus direction register port latch data bus pull-up control direction register port latch data bus pull-up control direction register port latch data bus pull-up control analog input pin selection bit a-d converter input direction register port latch data bus pull-up control
rev.1.01 aug 22, 2003 page 21 of 69 3826 group (a version) fig. 17 port block diagram (4) (18) port p6 1 (19) port p6 2 (20) port p6 3 serial i/o2 output serial i/o2 transmit end signal serial i/o2 synchronous clock selection bit serial i/o2 port selection bit pull-up control analog input pin selection bit a-d converter input p6 1 /s out2 p-channel output disable bit (21) com 0? com 3 (22) seg 0 ?seg 17 v l3 v l2 v l1 v ss v l2 /v l3 v l1 /v ss (23) port p7 0 int 0 input serial i/o2 synchronous clock selection bit serial i/o2 clock output serial i/o2 clock input serial i/o2 port selection bit synchronous clock output pin selection bit a-d converter input serial i/o2 clock output a-d converter input direction register port latch data bus pull-up control direction register port latch data bus analog input pin selection bit pull-up control direction register port latch data bus analog input pin selection bit serial i/o2 synchronous clock selection bit serial i/o2 port selection bit data bus the gate input signal of each transistor is controlled by the lcd duty ratio and the bias value. the voltage applied to the sources of p- channel and n-channel transistors is the controlled voltage by the bias value. synchronous clock output pin selection bit
rev.1.01 aug 22, 2003 page 22 of 69 3826 group (a version) interrupts i nterrupts occur by seventeen sources: seven external, nine inter- nal, and one software. when an interrupt request is accepted, the program branches to the interrupt jump destination address set in the vector address (see table 8). interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt is accepted if the corresponding interrupt request and enable bits are ?1? and the in- terrupt disable flag is ?0?. interrupt enable bits can be set to ?0? or ?1? by program. interrupt request bits can be set to ?0? by program, but cannot be set to ?1? by program. the brk instruction interrupt and reset cannot be disabled with any flag or bit. when the interrupt disable (i) flag is set to ?1?, all interrupt requests except the brk instruction interrupt and reset are not accepted. when several interrupt requests occur at the same time, the inter- rupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt jump destination address is read from the vector table into the program counter. 3. the interrupt disable flag is set to ?1? and the corresponding in- terrupt request bit is set to ?0?. notes1: vector addresses contain interrupt jump destination addresses. 2: reset is not an interrupt. reset has the higher priority than all interrupts. t able 8 interrupt vector addresses and priority remarks interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at completion of serial i/o1 data reception at completion of serial i/o1 transmit shift or when transmis- sion buffer is empty interrupt source low high priority v ector addresses (note 1) reset (note 2) int 0 int 1 serial i/o1 reception serial i/o1 transmission t imer x t imer y t imer 2 t imer 3 cntr 0 cntr 1 t imer 1 int 2 serial i/o2 key input (key-on wake-up) adt a-d conversion brk instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 at timer x underflow at timer y underflow at timer 2 underflow at timer 3 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer 1 underflow at detection of either rising or falling edge of int 2 input at completion of serial i/o2 data transmission or reception at falling of conjunction of input level for port p2 (at input mode) at falling edge of adt input at completion of a-d conversion at brk instruction execution non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) v alid when serial i/o1 is selected v alid when serial i/o1 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) v alid when serial i/o2 is selected external interrupt (valid at falling) v alid when adt interrupt is selected external interrupt (valid at falling) v alid when a-d interrupt is selected non-maskable software interrupt
rev.1.01 aug 22, 2003 page 23 of 69 3826 group (a version) fig. 18 interrupt control fig. 19 structure of interrupt-related registers notes on interrupts when setting the followings, the interrupt request bit may be set to ?1?. ?when switching external interrupt active edge related register: interrupt edge selection register (address 3a 16 ) t imer x mode register (address 27 16 ) t imer y mode register (address 28 16 ) ?when switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated related register: interrupt source selection bit of a-d control reg- ister (bit 6 of address 34 16 ) when not requiring for the interrupt occurrence synchronous with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ?0? (disabled). ? set the interrupt edge select bit (polarity switch bit) or the inter- rupt source selection bit. ? set the corresponding interrupt request bit to ?0? after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ?1? (enabled). i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t i n t e r r u p t d i s a b l e f l a g ( i ) brk inst ruct ion rese t in te rr upt request acceptance b 7 b 0 i nterrupt e d ge se l ect i on reg i ster i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 1 i n t e r r u p t e d g e s e l e c t i o n b i t i n t 2 i n t e r r u p t e d g e s e l e c t i o n b i t n o t u s e d ( ? 0 ? a t r e a d i n g ) ( i n t e d g e : a d d r e s s 0 0 3 a 1 6 ) i nterrupt r equest reg i ster 1 i n t 0 i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t b i t t i m e r x i n t e r r u p t r e q u e s t b i t t i m e r y i n t e r r u p t r e q u e s t b i t t i m e r 2 i n t e r r u p t r e q u e s t b i t t i m e r 3 i n t e r r u p t r e q u e s t b i t i nterrupt contro l reg i ster 1 i n t 0 i n t e r r u p t e n a b l e b i t i n t 1 i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o 1 t r a n s m i t i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t t i m e r y i n t e r r u p t e n a b l e b i t t i m e r 2 i n t e r r u p t e n a b l e b i t t i m e r 3 i n t e r r u p t e n a b l e b i t 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d (ireq 1 : a dd re ss 003 c 16 ) ( i c o n 1 : a d d r e s s 0 0 3 e 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 c n t r 0 i n t e r r u p t r e q u e s t b i t c n t r 1 i n t e r r u p t r e q u e s t b i t t i m e r 1 i n t e r r u p t r e q u e s t b i t i n t 2 i n t e r r u p t r e q u e s t b i t s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t k e y i n p u t i n t e r r u p t r e q u e s t b i t a d t / a d c o n v e r s i o n i n t e r r u p t r e q u e s t b i t n o t u s e d ( ? 0 ? a t r e a d i n g ) ( i r e q 2 : a d d r e s s 0 0 3 d 1 6 ) i nterrupt contro l reg i ster 2 cntr 0 i nterr upt ena bl e bi t cntr 1 interr upt enable bit time r 1 interr upt enable bit int 2 interrup t en able bit serial i/o2 interrupt enable bit key input interrupt enable bit adt/ad conversion interrupt enable bit not used (?0? at reading) (write ?0? to this bit) 0 : i nterrupts di sa bl e d 1 : interrupts enabled (icon 2 : a dd re ss 003 f 16 ) 0 : f a lli ng e d ge act i ve 1 : rising edge active b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 0
rev.1.01 aug 22, 2003 page 24 of 69 3826 group (a version) key input interrupt (key-on wake up) the key input interrupt is enabled when any of port p2 is set to in- put mode and the bit corresponding to key input control register is set to ?1?. a key input interrupt request is generated by applying ?l? level voltage to any pin of port p2 of which key input interrupt is en- abled. in other words, it is generated when and of input level goes from ?1? to ?0?. a connection example of using a key input in- terrupt is shown in figure 20, where an interrupt request is gener- ated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p2 0 ?p2 3 . fig. 20 connection example when using key input interrupt and port p2 block diagram p o r t p 2 0 l a t c h p o r t p 2 0 d i r e c t i o n r e g i s t e r = ? 0 ? p o r t p 2 1 l a t c h port p2 1 direction regist er = ?0? p o r t p 2 2 l a t c h port p2 2 direction regist er = ?0? port p2 3 latch port p2 3 direction regist er = ?0? p o r t p 2 4 l a t c h port p2 4 direction regist er = ?1? p o r t p 2 5 l a t c h p o r t p 2 5 d i r e c t i o n r e g i s t e r = ? 1 ? port p2 6 latch port p2 6 direction register = ?1? p o r t p 2 7 l a t c h port p2 7 direction register = ?1? p 2 0 i n p u t p2 1 input p 2 2 i n p u t p 2 3 i n p u t p2 4 output p 2 5 o u t p u t p 2 6 o u t p u t p 2 7 o u t p u t p u l l r e g i s t e r a b i t 7 p o r t p 2 i n p u t r e a d i n g c i r c u i t p o r t p x x ? l ? l e v e l o u t p u t ? p - c h a n n e l t r a n s i s t o r f o r p u l l - u p ? ? c m o s o u t p u t b u f f e r key i nput interrupt request p 2 7 ke y i n p u t c o n t r o l b i t p 2 6 k e y i n p u t c o n t r o l b i t ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? p2 5 key input co ntrol bit p 2 4 k e y i n p u t c o n t r o l b i t p 2 3 k e y i n p u t c o n t r o l b i t = ? 1 ? pull re gist er a bit 6 = ?1 ? p2 2 key input cont rol bit = ?1? p 2 1 k e y i n p u t c o n t r o l b i t = ? 1 ? p2 0 key input cont rol bit = ?1?
rev.1.01 aug 22, 2003 page 25 of 69 3826 group (a version) the key input interrupt is controlled by the key input control regis- ter and the port direction register. when enabling the key input interrupt, set ?1? to the key input control bit. a key input can be ac- cepted from pins set as the input mode in ports p2 0 ?p2 7 . fig. 21 structure of key input control register p 2 0 k ey i nput contro l bi t p2 1 key input control bit p2 2 key input control bit p2 3 key input control bit p2 4 key input control bit p2 5 key input control bit p2 6 key input control bit p2 7 key input control bit 0 : k e y i n p u t i n t e r r u p t d i s a b l e d 1 : k e y i n p u t i n t e r r u p t e n a b l e d k ey i nput contro l reg i ster (kic : ad dress 0015 16 ) b 7 b 0
rev.1.01 aug 22, 2003 page 26 of 69 3826 group (a version) timers the 3826 group has five timers: timer x, timer y, timer 1, timer 2, and timer 3. timer x and timer y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. all timers are down count timers. when the timer reaches ?0?, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit corresponding to that timer is set to ?1?. fig. 22 timer block diagram ?1? p5 5 /cntr 1 ?0? ? 1 0 ? ?00?,?01?,?11? p5 4 /cntr 0 q q t s ? 0 ? ?1? ? 0 ? q d ? 0 ? q d ?1? ? 0 ? ? 1 ? ? 1 0 ? q t s ? 0 ? ? 1 ? ? 0 ? ?1? ?1? p 4 3 / /t out x c i n ?0? ?1? c n t r 0 a c t i v e e d g e s w i t c h b i t t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t real time port control bit ?0? f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 w h e n = x c i n / 2 ) c n t r 1 a c t i v e e d g e s w i t c h b i t time r y stop control bit fall ing edge detect ion p e r i o d m e a s u r e m e n t m o d e time r y interrupt req uest pulse width hl continuously measurem ent mode rising edge detection t i m e r y o p e r a t i n g m o d e b i t s time r x interrupt req uest t i m e r x m o d e r e g i s t e r w r i t e s i g n a l p 4 3 d i r e c t i o n r e g i s t e r p u l s e o u t p u t m o d e p5 4 latch time r x stop control bit time r x wr ite control bit l a t c h time r x operat- ing mode bits ?00?,?01?,?11? pulse width measur ement mode c n t r 0 a c t i v e e d g e s w i t c h b i t pulse out put mode p5 4 direction register t o u t o u t p u t a c t i v e e d g e s w i t c h b i t ? 0 ? t i m e r 2 w r i t e c o n t r o l b i t time r 3 count source selection bit t i m e r 2 i n t e r r u p t r e q u e s t time r 3 inte rrupt req uest t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t t i m e r 1 i n t e r r u p t r e q u e s t d a t a b u s r e a l t i m e p o r t c o n t r o l b i t ? 1 ? r e a l t i m e p o r t c o n t r o l b i t ? 1 ? time r 3 latc h (8) t i m e r 3 r e g i s t e r ( 8 ) time r 1 latch (8) time r 1 register (8) time r 2 latc h (8) time r 2 register (8) timer x low-order register (8) time r x (low) latch (8) time r x (high) latch (8) time r y (low) latch (8) timer y (high) latch (8) l a t c h p 4 3 l a t c h f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 w h e n = x c i n / 2 ) f(x in )/16 (f(x cin )/16 when = x cin /2) f(x in )/16 (f(x cin )/16 when = x cin /2) f ( x i n ) / 1 6 ( f ( x c i n ) / 1 6 w h e n = x c i n / 2 ) p 5 2 / r t p 0 p 5 3 / r t p 1 rtp 0 data for real time port rtp 1 data for real time port p 5 2 d i r e c t i o n r e g i s t e r p 5 2 l a t c h p 5 3 d i r e c t i o n r e g i s t e r p 5 3 l a t c h timer x high-order register (8) timer y low-order register (8) t i m e r y h i g h - o r d e r r e g i s t e r ( 8 ) q t out / output selection bit t out / output enable bit t o u t / o u t p u t e n a b l e b i t
rev.1.01 aug 22, 2003 page 27 of 69 3826 group (a version) t imer x t imer x is a 16-bit timer and is equipped with the timer latch. the division ratio of timer x is given by 1/(n+1), where n is the value in the timer latch. timer x is a down-counter. when the contents of timer x reach ?0000 16 ?, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. when the timer underflows, the timer x interrupt request bit is set to ?1?. t imer x can be selected in one of four modes by the timer x mode register and can be controlled the timer x write and the real time port. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). (2) pulse output mode each time the timer underflows, a signal output from the cntr 0 pin is inverted. except for this, the operation in pulse output mode is the same as in timer mode. when using a timer in this mode, set the p5 4 /cntr 0 pin to output mode (set ?1? to bit 4 of port p5 direction register). (3) event counter mode the timer counts signals input through the cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the p5 4 / cntr 0 pin to input mode (set ?0? to bit 4 of port p5 direction reg- ister). (4) pulse width measurement mode the count source is f(x in )/16 (or f(x cin )/16 in low-speed mode). if cntr 0 active edge switch bit is ?0?, the timer counts while the input signal of cntr 0 pin is at ?h?. if it is ?1?, the timer counts while the input signal of cntr 0 pin is at ?l?. when using a timer in this mode, set the p5 4 /cntr 0 pin to input mode (set ?0? to bit 4 of port p5 direction register). read and write to timer x high-order, low-order registers when reading and writing to the timer x high-order and low-order registers, be sure to read/write both the timer x high- and low-or- der registers. when reading the timer x high-order and low-order registers, read the high-order register first. when writing to the timer x high-order and low-order registers, write the low-order register first. the timer x cannot perform the correct operation if the next operation is per- formed. ?write operation to the high- or low-order register before reading the timer x low-order register ?read operation from the high- or low-order register before writing to the timer x high-order register fig. 23 structure of timer x mode register t i m e r x m o d e r e g i s t e r ( t x m : a d d r e s s 0 0 2 7 1 6 ) t i m e r x w r i t e c o n t r o l b i t 0 : w r i t e v a l u e i n l a t c h a n d t i m e r 1 : w r i t e v a l u e i n l a t c h o n l y r e a l t i m e p o r t c o n t r o l b i t 0 : r e a l t i m e p o r t f u n c t i o n i n v a l i d 1 : r e a l t i m e p o r t f u n c t i o n v a l i d r t p 0 d a t a f o r r e a l t i m e p o r t r t p 1 d a t a f o r r e a l t i m e p o r t t i m e r x o p e r a t i n g m o d e b i t s b 5 b 4 00 : t i m e r m o d e 01 : p u l s e o u t p u t m o d e 10 : e v e n t c o u n t e r m o d e 11 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 0 a c t i v e e d g e s w i t c h b i t 0 : c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m ? h ? o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e ? h ? p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e f a l l i n g e d g e a c t i v e f o r c n t r 0 i n t e r r u p t 1 : c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m ? l ? o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e ? l ? p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e r i s i n g e d g e a c t i v e f o r c n t r 0 i n t e r r u p t t i m e r x s t o p c o n t r o l b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p b 7 b 0 t imer x write control which write control can be selected by the timer x write control bit (bit 0) of the timer x mode register (address 0027 16 ), writing data to both the latch and the timer at the same time or writing data only to the latch. when the operation ?writing data only to the latch? is selected, the value is set to the timer latch by writing data to the timer x register and the timer is updated at next underflow. after reset, the operation ?writing data to both the latch and the timer at the same time? is selected, and the value is set to both the latch and the timer at the same time by writing data to the timer x register. the write operation is independent of timer x count operation, operating or stopping. when the value is written in latch only, a value is simultaneously set to the timer x and the timer x latch if the writing in the high- order register and the underflow of timer x are performed at the same timing. unexpected value may be set in the high-order timer on this occasion. real time port control while the real time port function is valid, data for the real time port are output from ports p5 2 and p5 3 each time the timer x underflows. (however, if the real time port control bit is changed from ?0? to ?1? after set of the real time port data, data are output independent of the timer x operation.) if the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer x. before using this function, set the p5 2 /rtp 0 , p5 3 /rtp 1 pins to output mode (set ?1? to bits 2, 3 of port p5 direction register). note on cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit.
rev.1.01 aug 22, 2003 page 28 of 69 3826 group (a version) t imer y t imer y is a 16-bit timer and is equipped with the timer latch. the division ratio of timer y is given by 1/(n+1), where n is the value in the timer latch. timer y is a down-counter. when the contents of timer y reach ?0000 16 ?, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. when the timer underflows, the timer y interrupt request bit is set to ?1?. t imer y can be selected in one of four modes by the timer y mode register. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). (2) period measurement mode cntr 1 interrupt request is generated at rising or falling edge of cntr 1 pin input signal. simultaneously, the value in timer y latch is reloaded in timer y and timer y continues counting down. except for this, the operation in period measurement mode is the same as in timer mode. the timer value just before the reloading at rising or falling of cntr 1 pin input signal is retained until the next valid edge is input. the rising or falling timing of cntr 1 pin input signal can be discriminated by cntr 1 interrupt. when using a timer in this mode, set the p5 5 /cntr 1 pin to input mode (set ?0? to bit 5 of port p5 direction register). (3) event counter mode the timer counts signals input through the cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the p5 5 /cntr 1 pin to input mode (set ?0? to bit 5 of port p5 direction register). (4) pulse width hl continuously measure- ment mode cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. when using a timer in this mode, set the p5 5 /cntr 1 pin to input mode (set ?0? to bit 5 of port p5 direction register). note on cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the value of the cntr 1 active edge switch bit. however, in pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the value of cntr 1 active edge switch bit. fig. 24 structure of timer y mode register ti mer y mo d e reg i ster (tym : ad dress 0028 16 ) b 7 b 0 n o t u s e d ( ? 0 ? a t r e a d i n g ) t i m e r y o p e r a t i n g m o d e b i t s b 5b 4 00 : t i m e r m o d e 01 : p e r i o d m e a s u r e m e n t m o d e 10 : e v e n t c o u n t e r m o d e 11 : p u l s e w i d t h h l c o n t i n u o u s l y m e a s u r e m e n t m o d e c n t r 1 a c t i v e e d g e s w i t c h b i t 0 : c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e m e a s u r e t h e f a l l i n g e d g e t o f a l l i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e f a l l i n g e d g e a c t i v e f o r c n t r 1 i n t e r r u p t 1 : c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e m e a s u r e t h e r i s i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e r i s i n g e d g e a c t i v e f o r c n t r 1 i n t e r r u p t t i m e r y s t o p c o n t r o l b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p
rev.1.01 aug 22, 2003 page 29 of 69 3826 group (a version) t imer 1, timer 2, timer 3 t imer 1, timer 2, and timer 3 are 8-bit timers and is equipped with the timer latch. the count source for each timer can be selected by the timer 123 mode register. the division ratio of each timer is given by 1/(n+1), where n is the value in the timer latch. all timers are down-counters. when the contents of the timer reach ?00 16 ?, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. when the timer underflows, the interrupt request bit corresponding to that timer is set to ?1?. when a value is written to the timer 1 register and the timer 3 reg- ister, a value is simultaneously set as the timer latch and the timer. when the timer 1 register, the timer 2 register, or the timer 3 regis- ter is read, the count value of the timer can be read. t imer 2 write control which write can be selected by the timer 2 write control bit (bit 2) of the timer 123 mode register (address 0029 16 ), writing data to both the latch and the timer at the same time or writing data only to the latch. when the operation ?writing data only to the latch? is selected, the value is set to the timer 2 latch by writing data to the timer 2 register and the timer 2 is updated at next underflow. after reset, the operation ?writing data to both the latch and the timer at the same time? is selected, and the value is set to both the timer 2 latch and the timer 2 at the same time by writing data to the timer 2 register. if the value is written in latch only, a value is simultaneously set to the timer 2 and the timer 2 latch when the writing in the high- order register and the underflow of timer 2 are performed at the same timing. t imer 2 output control when the timer 2 (t out ) output is enabled by the t out / output enable bit and the t out / output selection bit, an inversion signal from the t out pin is output each time timer 2 underflows. in this case, set the p4 3 / /t out pin to output mode (set ?1? to bit 3 of port p4 direction register). note on timer 1 to timer 3 when the count source of timers 1 to 3 is changed, the timer counting value may become arbitrary value because a thin pulse is generated in count input of timer. if timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may become undefined value because a thin pulse is generated in timer 1 output. therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. fig. 25 structure of timer 123 mode register t out output act i ve e d ge sw i tc h bi t 0 : start at ?h? output 1 : start at ?l? output t out / output enablel bit 0 : t out / output disabled 1 : t out / output enabled time r 2 wr ite co ntrol bit 0 : write data in latch and counter 1 : write data in latch only timer 2 count source selection bit 0 : timer 1 output signal 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 3 count source selection bit 0 : timer 1 output signal 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 1 count source selection bit 0 : f(x in )/16 (or f(x cin )/16 in low-speed mode) 1 : f(x cin ) not used (?0? at reading) ti mer 123 mo d e reg i ster (t123m :address 0029 16 ) n ote: s ystem c l oc k i s f(x cin )/ 2 i n t h e l ow-spee d mo d e. b 7 b 0
rev.1.01 aug 22, 2003 page 30 of 69 3826 group (a version) serial i/o serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode is selected by setting the se- rial i/o1 mode selection bit of the serial i/o1 control register to ?1?. for clock synchronous serial i/o mode, the transmitter and the re- ceiver must use the same clock as an operation clock. when an internal clock is selected as an operation clock, transmit or receive is started by a write signal to the transmit buffer regis- ter. when an external clock is selected as an operation clock, serial i/ o1 becomes the state where transmit or receive can be performed by a write signal to the transmit buffer register. transmit and re- ceive are started by input of an external clock. fig. 26 block diagram of clock synchronous serial i/o1 fig. 27 operation of clock synchronous serial i/o1 function p 4 6 / s c l k 1 p 4 7 / s r d y 1 p 4 4 / r x d p 4 5 /t x d x i n 1 / 4 1 / 4 f / f serial i /o1 status register s e r i a l i / o 1 c o n t r o l r e g i s t e r r e c e i v e b u f f e r r e g i s t e r add re ss 0018 16 receive shift register r e c e i v e b u f f e r f u l l f l a g ( r b f ) r ece i ve i nterrupt request receive cl o ck control circuit shif t c l oc k s er i a l i/o 1 sync h rono us clock selection bit fr equency division ratio 1/(n+1) ba ud rate generator add re ss 001 c 16 brg c ount sour ce se l ect i on bi t f a l l i n g - e d g e d e t e c t o r d ata b us a d d r e s s 0 0 1 8 1 6 s h i f t c l o c k t r ansm i t s hif t reg i ster s hif t comp l et i on fl ag (tsc) t r ansm i t b u ff er empty fl ag (t be) t r a n s m i t i n t e r r u p t r e q u e s t t r ansm i t i nterr upt sour ce se l ect i on bi t add re ss 0019 16 d ata b us add re ss 001 a 16 transmit buffer register transmit shift register transmit clock control circuit r e c e i v e e n a b l e s i g n a l s r d y 1 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 r b f = ? 1 ? t s c = ? 1 ? t b e = ? 0 ? tbe = ? 1 ? tsc = ?0? t r a n s m i t a n d r e c e i v e s h i f t c l o c k ( 1 / 2 t o 1 / 2 0 4 8 o f t h e i n t e r n a l c l o c k , o r a n e x t e r n a l c l o c k ) s e r i a l o u t p u t t x d s e r i a l i n p u t r x d w r i t e s i g n a l t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 1 8 1 6 ) o verrun erro r (oe) detect ion n otes 1 : a f t e r d a t a t r a n s f e r r i n g , t h e t x d p i n k e e p s d 7 o u t p u t v a l u e . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = ? 0 ? , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a c a n b e o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : s e l e c t t h e s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t f a c t o r b e t w e e n w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d ( t b e = ? 1 ? ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = ? 1 ? ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 4 : t h e s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t o c c u r s w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s ? 1 ? . d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 ( n o t e 1 ) ( n o t e 3 ) ( n o t e 2 ) (n ote 3 ) ( n o t e 4 )
rev.1.01 aug 22, 2003 page 31 of 69 3826 group (a version) (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) is selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register to ?0?. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address (0018 16 ) in memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. the transmit buffer can also hold the next data to be transmitted during transmitting, and the receive buffer register can hold re- ceived one-byte data while the next one-byte data is being re- ceived. fig. 28 block diagram of uart serial i/o1 fig. 29 operation of uart serial i/o1 function x in 1 / 4 o e p e f e 1 / 16 1 / 16 d ata b us r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t b a u d r a t e g e n e r a t o r f r equency di v i s i on rat i o 1 /( n+1 ) add re ss 001 c 16 st/sp/pa generator tr ansmit buffer register d a t a b u s t r ansm i t s hif t reg i ster add re ss 0018 16 t r ansm i t s hif t reg i ster s hif t comp l et i on fl ag (tsc) t r ansm i t b u ff er empty fl ag (t be) t r ansm i t i nterr upt request add re ss 0019 16 s t d e t e c t o r s p d e t e c t o r u a r t c o n t r o l r e g i s t e r add re ss 001 b 16 c h a r a c t e r l e n g t h s e l e c t i o n b i t a d d r e s s 0 0 1 a 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t t r ansm i t i nterr upt sour ce se l ect i on bit s e r i a l i / o 1 s y n c h r o n i z a t i o n c l o c k s e l e c t i o n b i t cl oc k contro l c i rcu it c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s s e r i a l i / o 1 c o n t r o l r e g i s t e r p 4 6 / s c l k 1 s er i a l i/o 1 status reg i ste r p 4 4 / r x d p 4 5 /t x d t s c = ? 0 ? t b e = ? 1 ? r b f = ? 0 ? t b e = ? 0 ? t b e = ? 0 ? r b f = ? 1 ? r b f = ? 1 ? s t d 0 d 1 s p d 0 d 1 s t s p t b e = ? 1 ? t s c = ? 1 ? ? s t d 0 d 1 s p d 0 d 1 s t s p t r a n s m i t b u f f e r r e g i s t e r w r i t e s i g n a l ? g e n e r a t e d a t 2 n d b i t i n 2 - s t o p - b i t m o d e 1 s t a r t b i t 7 o r 8 d a t a b i t s 1 o r 0 p a r i t y b i t 1 o r 2 s t o p b i t ( s ) 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s ? 1 ? ( a t 1 s t s t o p b i t f o r r e c e p t i o n ) . 2 : t h e s e r i a l i / o 1 r e c e i v e i n t e r r u p t r e q u e s t o c c u r s w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s ? 1 ? . 3 : s e l e c t t h e s e r i a l i / o 1 t r a n s m i t i n t e r r u p t r e q u e s t o c c u r r e n c e f a c t o r b e t w e e n w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d ( t b e = ? 1 ? ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = ? 1 ? ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . n o t e s s e r i a l o u t p u t t x d s e r i a l i n p u t r x d r e c e i v e b u f f e r r e g i s t e r r e a d s i g n a l t r a n s m i t o r r e c e i v e c l o c k ( n o t e s 1 , 2 ) ( n o t e s 1 , 2 )
rev.1.01 aug 22, 2003 page 32 of 69 3826 group (a version) [transmit buffer/receive buffer register (tb/ rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer register is write- only and the receive buffer register is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer regis- ter is ?0?. [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is set to ?0? when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set to ?1?. a write signal to the serial i/o1 status register sets all the error flags (oe, pe, fe, and se) (bit 3 to bit 6, respectively) to ?0?. writing ?0? to the serial i/o1 enable bit (sioe) also sets all the status flags to ?0?, includ- ing the error flags. all bits of the serial i/o1 status register are set to ?0? at reset, but if the transmit enable bit of the serial i/o1 control register has been set to ?1?, the transmit shift register shift completion flag and the transmit buffer empty flag become ?1?. [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register contains eight control bits for the serial i/o1 function. [uart control register (uartcon)] 001b 16 the uart control register consists of the bits which set the data format of an data transmit and receive, and the bit which sets the output structure of the p4 5 /t x d pin. [baud rate generator (brg)] 001c 16 the baud rate generator is the 8-bit counter equipped with a reload register. set the division value of the brg count source to the baud rate generator. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. notes on serial i/o when setting the transmit enable bit to ?1?, the serial i/o1 transmit interrupt request bit is automatically set to ?1?. when not requiring the interrupt occurrence synchronous with the transmission en- abled, take the following sequence. ? set the serial i/o1 transmit interrupt enable bit to ?0? (disabled). ? set the transmit enable bit to ?1?. ? set the serial i/o1 transmit interrupt request bit to ?0? after 1 or more instructions have been executed. ? set the serial i/o1 transmit interrupt enable bit to ?1? (enabled).
rev.1.01 aug 22, 2003 page 33 of 69 3826 group (a version) fig. 30 structure of serial i/o1 control registers brg c ount sour ce se l ect i on bi t (css) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected. brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is se lected. external clock input divided by 16 when uart is sele cted. s rdy1 output enable bit (srdy) 0: p4 7 pi n ope ra tes as ordinary i/o pin 1: p4 7 pin operates as s rdy1 output pin tr ansmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shi ft operation is completed tr ansmit en able bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: a synchronous serial i/o (uart) 1: clo ck synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p4 4 ?p4 7 o perate as ordinary i/o pins) 1: serial i/o1 enabled (pins p4 4 ?p4 7 o perate as serial i/o pins) s er i a l i/o 1 contro l reg i ster (sio1con : ad dress 001a 16 ) b 7b 0 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( ? 1 ? a t r e a d i n g ) s e r i a l i / o 1 s t a t u s r e g i s t e r ( s i o 1 s t s : a d d r e s s 0 0 1 9 1 6 ) b 7b 0 u a r t c o n t r o l r e g i s t e r ( u a r t c o n : a d d r e s s 0 0 1 b 1 6 ) ch aracter l engt h se l ect i on bi t ( ch as) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity che cking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d p-chan nel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) not used (?1? at reading) b7 b0
rev.1.01 aug 22, 2003 page 34 of 69 3826 group (a version) serial i/o2 serial i/o2 can be used only for clock synchronous serial i/o. for serial i/o2, the transmitter and the receiver must use the same clock as a synchronous clock. when an internal clock is se- lected as a synchronous clock, the serial i/o2 is initialized and, transmit and receive is started by a write signal to the serial i/o2 register. when an external clock is selected as an synchronous clock, the serial i/o2 counter is initialized by a write signal to the serial i/o2 register, serial i/o2 becomes the state where transmission or re- ception can be performed. write to the serial i/o2 register while s clk21 is ?h? state when an external clock is selected as an syn- chronous clock. either p6 2 /s clk21 or p6 3 /s clk22 pin can be selected as an output pin of the synchronous clock. in this case, the pin that is not se- lected as an output pin of the synchronous clock functions as a i/ o port. [serial i/o2 control register (sio2con)] 001d16 the serial i/o2 control register contains eight control bits for the serial i/o2 functions. after setting to this register, write data to the serial i/o2 register and start transmit and receive. fig. 31 structure of serial i/o2 control register fig. 32 block diagram of serial i/o2 function s e r i a l i / o 2 c o n t r o l r e g i s t e r ( s i o 2 c o n : a d d r e s s 0 0 1 d 1 6 ) b 7 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t b i t s 0 0 0 : f ( x i n ) / 8 0 0 1 : f ( x i n ) / 1 6 0 1 0 : f ( x i n ) / 3 2 0 1 1 : f ( x i n ) / 6 4 1 0 0 : 1 0 1 : 1 1 0 : f ( x i n ) / 1 2 8 1 1 1 : f ( x i n ) / 2 5 6 s e r i a l i / o 2 p o r t s e l e c t i o n b i t 0 : i / o p o r t 1 : s o u t 2 , s c l k 2 1 / s c l k 2 2 s i g n a l o u t p u t p 6 1 / s o u t 2 p - c h a n n e l o u t p u t d i s a b l e b i t 0 : c m o s o u t p u t ( i n o u t p u t m o d e ) 1 : n - c h a n n e l o p e n - d r a i n o u t p u t ( i n o u t p u t m o d e ) t r a n s f e r d i r e c t i o n s e l e c t i o n b i t 0 : l s b f i r s t 1 : m s b f i r s t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k s y n c h r o n o u s c l o c k o u t p u t p i n s e l e c t i o n b i t 0 : s c l k 2 1 1 : s c l k 2 2 b 0 b 2 b 1 b 0 do not select x in ?1? ? 0 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? s c l k 2 ( n o t e ) 1 / 8 1 / 1 6 1 / 3 2 1 / 6 4 1 / 1 2 8 1 / 2 5 6 d a t a b u s s e r i a l i / o 2 i n t e r r u p t r e q u e s t s e r i a l i / o 2 p o r t s e l e c t i o n b i t s e r i a l i / o 2 c o u n t e r ( 3 ) s e r i a l i / o 2 r e g i s t e r ( 8 ) s y n c h r o n o u s c i r c u i t s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t e x t e r n a l c l o c k i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t b i t s d i v i d e r p 6 3 l a t c h p 6 3 / s c l k 2 2 p 6 2 / s c l k 2 1 p 6 1 / s o u t 2 p 6 0 / s i n 2 p 6 2 l a t c h p 6 1 l a t c h ( n o t e ) n o t e : i t i s s e l e c t e d b y t h e s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t , t h e s y n c h r o n o u s c l o c k o u t p u t p i n s e l e c t i o n b i t , a n d t h e s e r i a l i / o 2 p o r t s e l e c t i o n b i t .
rev.1.01 aug 22, 2003 page 35 of 69 3826 group (a version) fig. 33 timing of serial i/o2 function d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 s y n c h r o n o u s c l o c k ( n o t e 1 ) serial i/o2 output s out2 serial i/o2 input s in2 serial i/o2 r egister write signal (notes 2, 3) s e r i a l i / o 2 i n t e r r u p t r e q u e s t b i t = ? 1 ? 1 : w h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e s y n c h r o n o u s c l o c k , t h e d i v i d e r a t i o c a n b e s e l e c t e d b y s e t t i n g b i t s 0 t o 2 o f t h e s e r i a l i / o 2 c o n t r o l r e g i s t e r . 2 : w h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e s y n c h r o n o u s c l o c k , t h e s o u t 2 p i n g o e s t o h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n . 3 : w h e n t h e e x t e r n a l c l o c k i s s e l e c t e d a s t h e s y n c h r o n o u s c l o c k , t h e s o u t 2 p i n k e e p s d 7 o u t p u t l e v e l a f t e r t r a n s f e r c o m p l e t i o n . h o w e v e r , i f s y n c h r o n o u s c l o c k s i n p u t a r e c a r r i e d o n , t h e t r a n s m i t d a t a w i l l b e o u t p u t c o n t i n u o u s l y f r o m t h e s o u t 2 p i n b e c a u s e s h i f t s o f s e r i a l i / o 2 s h i f t r e g i s t e r i s c o n t i n u e d a s l o n g a s s y n c h r o n o u s c l o c k s a r e i n p u t . n o t e s serial i/o2 operating the serial i/o2 counter is initialized to ?7? by writing to the serial i/o2 register. after writing, whenever a synchronous clock changes from ?h? to ?l?, data is output from the s out2 pin. moreover, whenever a syn- chronous clock changes from ?l? to ?h?, data is taken in from the s in2 pin, and 1 bit shift of the serial i/o2 register is carried out si- multaneously. when the internal clock is selected as a synchronous clock, it is as follows if a synchronous clock is counted 8 times. ?serial i/o2 counter = ?0? ?synchronous clock stops in ?h? state ?serial i/o2 interrupt request bit = ?1? the s out2 pin is in a high impedance state after transfer is com- pleted. when the external clock is selected as a synchronous clock, if a synchronous clock is counted 8 times, the serial i/o2 interrupt re- quest bit is set to ?1?, and the s out2 pin holds the output level of d 7 . however, if a synchronous clock continues being input, the shift of the serial i/o2 register is continued and transmission data continues being output from the s out2 pin.
rev.1.01 aug 22, 2003 page 36 of 69 3826 group (a version) pulse width modulation (pwm) the 3826 group has a pwm function with an 8-bit resolution, using f(x in ) or f(x in )/2 as a count source. data setting the pwm output pins are shared with ports p5 0 and p5 1 . set the pwm period by the pwm prescaler, and set the period during which the output pulse is an ?h? by the pwm register. if pwm count source is f(x in ) and the value in the pwm prescaler is n and the value in the pwm register is m (where n = 0 to 255 and m = 0 to 255) : pwm period = 255 ? (n+1)/f(x in ) = 31.875 ? (n+1) s (when f(x in ) = 8 mhz) output pulse ?h? period = pwm period ? m/255 = 0.125 ? (n+1) ? m s (when f(x in ) = 8 mhz) pwm operation when either bit 1 (pwm 0 function enable bit) or bit 2 (pwm 1 func- tion enable bit) of the pwm control register or both bits are enabled, operation starts from initializing status, and pulses are output starting at ?h?. when one pwm output is enabled and that the other pwm output is enabled, pwm output which is enabled to output later starts pulse output from halfway of pwm period (see figure 37). when the pwm register or pwm prescaler is updated during pwm output, the pulses will change in the cycle after the one in which the change was made. fig. 34 timing of pwm cycle fig. 35 block diagram of pwm function 31.875 ? m ? (n+1) 255 s t = [31.875 ? (n+1)] s pwm output m: contents of pwm register n : contents of pwm prescaler t : pwm cycle (when f(x in ) = 8 mhz) d a t a b u s c ount source selecti on bit ? 0 ? ? 1 ? p w m p r e s c a l e r p r e - l a t c h p w m r e g i s t e r p r e - l a t c h pwm pre scaler latch p w m r e g i s t e r l a t c h t rans f er contro l c i rcu i t p w m c i r c u i t 1 / 2 x i n pwm 0 f unct i on enable bit p 5 1 / p w m 1 pwm pre sca l er p w m 1 f u n c t i o n e n a b l e b i t p o r t p 5 1 l a c t h p o r t p 5 0 l a c t h p 5 0 / p w m 0
rev.1.01 aug 22, 2003 page 37 of 69 3826 group (a version) fig. 37 pwm output timing when pwm register or pwm prescaler is changed fig. 36 structure of pwm control register b 7 b 0 p w m c o n t r o l r e g i s t e r ( p w m c o n : a d d r e s s 0 0 2 b 1 6 ) c o u n t s o u r c e s e l e c t i o n b i t 0: f ( x i n ) 1: f ( x i n ) / 2 p w m 0 f u n c t i o n e n a b l e b i t 0: p w m 0 d i s a b l e d 1: p w m 0 e n a b l e d p w m 1 f u n c t i o n e n a b l e b i t 0: p w m 1 d i s a b l e d 1: p w m 1 e n a b l e d n o t u s e d ( ? 0 ? a t r e a d i n g ) t t2 c b t pwm register write signal pwm prescaler write signal (changes from ?a? to ?b? during ?h? period) (changes from ?t? to ?t2? during pwm period) pwm (internal) a b t c t2 = stop pwm 0 function enable bit pwm 1 function enable bit pwm 0 output port port pwm 1 output port stop port when the contents of the pwm register or pwm prescaler have changed, the pwm output will change from the next period after the change.
rev.1.01 aug 22, 2003 page 38 of 69 3826 group (a version) fig. 39 a-d converter block diagram a-d converter [a-d conversion register (ad)] 0034 16 the a-d conversion registers are read-only registers that store the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. [a-d control register (adcon)] 0034 16 the a-d control register controls the a-d conversion process. bits 0 to 2 of this register select specific analog input pins. bit 3 indi- cates the completion of an a-d conversion. the value of this bit re- mains at ?0? during an a-d conversion, then it is set to ?1? when the a-d conversion is completed. writing ?0? to this bit starts the a-d conversion. bit 4 is the v ref input switch bit which controls connection of the resistor ladder and the reference voltage input pin (v ref ). the resistor ladder is always connected to v ref when bit 4 is set to ?1?. when bit 4 is set to ?0?, the resistor ladder is cut off from v ref except for a-d conversion performed. when bit 5, which is the ad external trigger valid bit, is set to ?1?, a-d conversion starts also by a falling edge of an adt input. when using an a-d external trigger, set the p5 7 /adt pin to input mode (set ?0? to bit 7 of port p5 direc- tion register). comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref by 256 (when 8-bit a-d mode) or 1024 (when 10- bit a-d mode), and outputs the divided voltages. channel selector the channel selector selects one of the input ports p6 7 /an 7 ?p6 0 /an 0 . comparator and control circuit the comparator and control circuit compare an analog input volt- age with the comparison voltage and store the result in the a-d conversion register. when an a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad converter interrupt request bit to ?1?. note that because the comparator consists of a capacitor coupling, set f(x in ) to 500 khz or more during an a-d conversion. use the clock divided from the main clock f(x in ) as the system clock . fig. 38 structure of a-d converter-related registers a-d control register (adcon : address 0034 16 ) ad conversion completion bit 0 : conversion in progress 1 : conversion completed analog input pin selection bits b2b1b0 0 0 0 : p6 0 /an 0 0 0 1 : p6 1 /an 1 0 1 0 : p6 2 /an 2 0 1 1 : p6 3 /an 3 1 0 0 : p6 4 /an 4 1 0 1 : p6 5 /an 5 1 1 0 : p6 6 /an 6 1 1 1 : p6 7 /an 7 v ref input switch bit 0 : auto 1 : on ad external trigger valid bit 0 : a-d external trigger invalid 1 : a-d external trigger valid b7 b0 interrupt source selection bit 0 : interrupt request at a-d conversion completed 1 : interrupt request at adt input falling not used (?0? at reading) comparator a-d control circuit adt/a-d interrupt request av ss v re p6 0 /s in2 /an 0 data bus a-d control register b 7 b 0 a-d conversion register resistor ladder channel selector p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /s clk22 /an 3 p6 2 /s clk21 /an 2 p6 1 /s out2 /an 1 p5 7 /adt/da 2 8 3 (address 0035 16 )
rev.1.01 aug 22, 2003 page 39 of 69 3826 group (a version) d-a converter the 3826 group has a d-a converter with 8-bit resolution and 2 channels (da 1 , da 2 ). the d-a converter is started by setting the dtmf/da 1 selection bit and the ctcss/da 2 selection bit to ?0? and setting the value in the d-a conversion register. when the dtmf/da 1 output enable bit and the ctcss/da 2 output enable bit is set to ?1?, the result of d-a conversion is output from the corresponding da 1 p in or da 2 pin. when using the d-a converter, set the p5 6 /da 1 pin and the p5 7 /da 2 pin to input mode (set ?0? to bits 6, 7 of port p5 direction register) and the pull-up resistor should be in the off state previ- ously. the output analog voltage v is determined by the value n (base 10) in the d-a conversion register as follows: v=v ref ? n/256 (n=0 to 255) where v ref is the reference voltage. at reset, the d-a conversion registers are set to ?00 16 ?, the dtmf/ da 1 output enable bit and the ctcss/da 2 output enable bit are set to ?0?, and the p5 6 /da 1 pin and the p5 7 /da 2 pin goes to high impedance state. the da converter is not buffered, so connect an external buffer when driving a low-impedance load. note on applied voltage to v ref pin when the p5 6 /da 1 pin and the p5 7 /da 2 pin are used as an i/o port, be sure to apply vcc to v ref pin. when these pins are used as d-a conversion output pins, the vcc level is recommended for the applied voltage to v ref pin. when the voltage below vcc level is applied, the d-a conversion accuracy may be worse. fig. 40 structure of d-a control register fig. 41 block diagram of d-a converter b7 b0 d-a control register (dacon : address 0036 16 ) dtm f/da 1 output enable bit 0 : disabled 1 : enabled ctcss timer write control bit 0 : write value in latch only 1 : write value in latch and counter high/low group timer write control bit 0 : write value in latch only 1 : write value in latch and counter high group rom data selection bit 0 : sine wave 1 : ?0? fixed low group rom data selection bit 0 : sine wave 1 : ?0? fixed ctcss/da 2 selection bit 0 : da2 function 1 : ctcss function dtmf/da 1 selection bit 0 : da1 function 1 : dtmf function ctcss/da 2 output enable bit 0 : disabled 1 : enabled p5 6 /da 1 p5 7 /da 2 5-bit adder selector low group rom 5bit ? 32 selector 8-bit timer 8-bit timer x in /2 ctcss rom 8bit ? 64 10-bit timer selector high group rom 5bit ? 32 * selector selector data bus d-a1 conversion register (8) da 1 output enable bit da 2 out p ut enable bit data bus r-2r resistor ladder r-2r resistor ladder d-a2 conversion register (8) when dtmf is selected, the high-order 6 bits are automatically set as the dtmf output. the low-order 2 bits is set by writing data to the d-a1 conversion register. *
rev.1.01 aug 22, 2003 page 40 of 69 3826 group (a version) dtmf function (dual tone multi frequency) dtmf function is used to output the result which generated auto- matically the waveform of sine wave of two kinds of different frequency, and added two kinds of this sine wave as an analog value. dtmf output waveform can be output from da 1 pin. dtmf wave- form is output by setting ?1? (enabled) to the dtmf/da 1 output enable bit (bit 0 of address 0036 16 ), and setting ?1? to the dtmf/ da 1 selection bit (bit 2 of address 0036 16 ). at this time, set ?0? (in- put state) to the direction register of ports p5 6 /da 1 pin and pull-up resistor to be off state. in order to set two kinds of frequency which generates dtmf waveform, write a value in the dtmf high group timer and the dtmf low group timer, respectively. the value written in each above-mentioned timer is n, the sine wave of the following fre- quency can be generated. f = (hz) set ?06 16 ? or more to the dtmf high group timer and the dtmf low group timer. after reset release, ?06 16 ? is automatically set to them. f(x in )/2 (n+1) ? 32 the digital value for one period of high group and low group out- put is shown in figure 42. dtmf output is automatically input to high-order 6 bits of the d-a1 conversion register as 6-bit d-a data. the low-order 2 bits of the d-a1 conversion register are fixed to the value written in the d-a1 conversion register. moreover, only the sine wave of high group can be output by set- ting ?1? to the bit 4 of the d-a control register. by setting ?1? to the bit 5 of the d-a control register similarly, only the sine wave of low group can be output. writing to the dtmf high group timer and the dtmf low group timer can also be changed to ?writing to latch and timer simultaneously? by setting ?1? to the bit 6 of the d-a con trol register. ?writing to only latch? is set after reset release. if the d-a1 conversion register is read when the dtmf function is selected,the digital value of dtmf output can be read. fig. 42 waveform data of high group and low group d-a 1 value (8bit) * 0 5 10 15 20 25 30 14 16 28 16 3c 16 50 16 64 16 78 16 0 16 0 5 10 15 20 25 30 d-a 1 value (8bit) * 14 16 28 16 3c 16 50 16 64 16 78 16 0 16 d-a data of low group waveform (1 period) for dtmf d-a data of high group waveform (1 period) for dtmf * this is the value set to d-a1 conversion register when the low-order 2 bits are ?0?. conversion time of high group rom conversion time of low group rom
rev.1.01 aug 22, 2003 page 41 of 69 3826 group (a version) low groupt frequency, high group frequency low group frequency and high group frequency are as follows. (1) low group frequency ? 697 hz ? 770 hz ? 852 hz ? 941 hz (2) high group frequency ? 1209 hz ? 1336 hz ? 1477 hz ? 1633 hz t able 9 shows the example of frequency accuracy (at f(x in )=4 mhz). fig. 43 key matrix of telephone and rating frequency t able 9 example of frequency accuracy (at f(x in ) = 4 mhz) rating frequency (hz) 697 770 852 941 1209 1336 1477 1633 n (timer value) 89 80 72 65 51 46 41 37 error frequency (hz) ?2.6 1.6 4.2 5.9 ?7.1 ?6.3 1 1.1 1 1.7 deviation (%) ?0.367 0.208 0.488 0.630 ?0.580 ?0.460 0.750 0.720 output frequency (hz) 694.4 771.6 856.2 946.9 1201.9 1329.7 1488.1 1644.7 1 2 3 4 5 6 b 7 8 9 * 0 # a c d 697hz 770hz 852hz 941hz 1209hz 1336hz 1477hz 1633hz low group frequency high group frequency
rev.1.01 aug 22, 2003 page 42 of 69 3826 group (a version) ctcss function (continuous tone-controlled squelch system) the ctcss function is used to generate the sine wave of single frequency automatically. the ctcss output waveform can be out- put from da 2 pin. ctcss waveform is outputted by setting ?1? to the ctcss/da 2 output enable bit (bit 1 of address 0036 16 ), and setting ?1? to the ctcss/da 2 selection bit (bit 3 of address 0036 16 ). in order to set the frequency of ctcss output, value is written in the ctcss timer. the ctcss timer consists of a 10-bit timer. when writing a value to the ctcss timer, write the low-or- der byte first. rating frequency (hz) 67.0 77.0 88.5 100.0 107.2 1 14.8 123.0 131.8 141.3 151.4 162.2 173.8 186.2 203.5 218.1 233.6 250.3 n (timer value) 465 405 352 312 291 271 253 236 220 205 192 179 167 153 142 133 124 error frequency (hz) 0.06 ?0.03 0.027 ?0.16 ?0.18 0.09 0.03 0.06 0.10 0.30 ?0.28 ?0.19 ?0.19 ?0.58 0.43 ?0.39 ?0.30 deviation (%) 0.089 ?0.038 0.030 ?0.160 ?0.167 0.078 0.026 0.043 0.073 0.198 ?0.174 ?0.109 ?0.101 ?0.284 0.198 ?0.167 ?0.120 output frequency (hz)] 67.06 76.97 88.53 99.84 107.02 1 14.89 123.03 131.86 141.40 151.70 161.92 173.61 186.01 202.92 218.53 233.20 250.00 t able 10 example of frequency accuracy (at f(x in ) = 4 mhz) f (x in )/2 (n+1) ? 64 vcc 2 when reading a value from the ctcss timer, read the high-order byte first. by the value written in the ctcss timer is n, the sine wave of the following frequency is generated. f = (hz) set ?006 16 ? or more to the ctcss timer. ?00 16 ? is automatically set to the high-order of the ctcss timer and ?06 16 ? is automati- cally set to the low-order of the ctcss timer after reset release. the amplitude of ctcss output is obtained by the following for- mula. c = if the d-a2 conversion register is read when the ctcss function is selected, the digital value of ctcss output can be read. t able 10 shows the example of frequency accuracy (at f(x in ) = 4 mhz). fig. 44 equivalent connection circuit of d-a converter a v s s v r e f ? 0 ? ? 1 ? m s b ? 0 ? ? 1 ? r 2 r r 2r r 2r r 2 r r 2 r r 2r r 2 r2r l s b 2 r da i d - a i c o n v e r s i o n r e g i s t e r d a i o u t p u t e n a b l e b i t
rev.1.01 aug 22, 2003 page 43 of 69 3826 group (a version) lcd drive control circuit the 3826 group has the liquid crystal display (lcd) drive control circuit consisting of the following. ? lcd display ram ? segment output enable register ? lcd mode register ? v oltage multiplier ? selector ? t iming controller ? common driver ? segment driver ? bias control circuit a maximum of 40 segment output pins and 4 common output pins can be used. up to 160 pixels can be controlled for lcd display. when the lcd fig. 45 structure of segment output enable register and lcd mode register enable bit is set to ?1? (lcd on) after data is set in the lcd mode register, the segment output enable register and the lcd display ram, the lcd drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the lcd panel. t able 11 maximum number of display pixels at each duty ratio duty ratio maximum number of display pixel 80 dots or 8 segment lcd 10 digits 120 dots or 8 segment lcd 15 digits 160 dots or 8 segment lcd 20 digits 2 3 4 s egment output ena bl e bi t 0 0 : output ports p3 0 ?p3 5 1 : segment output seg 18 ? seg 23 segment output enable bit 1 0 : output ports p3 6 , p3 7 1 : segment output seg 24 ,seg 25 segment output enable bit 2 0 : i/o ports p0 0 ?p0 5 1 : segment output seg 26 ? seg 31 segment output enable bit 3 0 : i/o ports p0 6 ,p0 7 1 : segment output seg 32 ,seg 33 segment output enable bit 4 0 : i/o port p1 0 1 : segment output seg 34 segment output enable bit 5 0 : i/o ports p1 1 ?p1 5 1 : segment output seg 35 ? seg 39 lcd output enable bit 0 : disabled 1 : enabled not used (?0? at reading) (write ?0? to this bit at writ ing.) s e g m e n t o u t p u t e n a b l e r e g i s t e r ( s e g : a d d r e s s 0 0 3 8 1 6 ) b 7 b 0 l c d m o d e r e g i s t e r ( l m : a d d r e s s 0 0 3 9 1 6 ) d uty rat i o se l ect i on bi ts b 1b0 0 0 : not used 0 1 : 2 duty (use com 0 , com 1 ) 1 0 : 3 duty (use com 0 ?com 2 ) 1 1 : 4 duty (use com 0 ?com 3 ) bias control bit 0 : 1/3 bias 1 : 1/2 bias lcd enab le bit 0 : lcd off 1 : lcd on voltage multiplier control bit 0 : volt age mult iplier disable 1 : volt age multip lier en able l cd circuit di vider division ratio selection bits b 6b5 0 0 : clo ck input 0 1 : 2 division of clock in put 1 0 : 4 division of clock in put 1 1 : 8 division of clock in put l cdck count source selection bit (note) 0 : f(x cin )/32 1 : f(x in )/81 92 (f(x cin )/8192 in low-speed mode) n o t e : l c d c k i s a c l o c k f o r a l c d t i m i n g c o n t r o l l e r . b 7 b 0 0
rev.1.01 aug 22, 2003 page 44 of 69 3826 group (a version) fig. 46 block diagram of lcd controller/driver d a t a b u s t i m i n g c o n t r o l l e r l c d d i v i d e r f ( x i n ) / 8 1 9 2 ( f ( x c i n ) / 8 1 9 2 i n l o w - s p e e d m o d e ) f ( x c i n ) / 3 2 c o m 0 c o m 1 c o m 2 c o m 3 v s s v l 1 v l 2 v l 3 s e g 3 s e g 2 s e g 1 s e g 0 a d d r e s s 0 0 4 0 1 6 a d d r e s s 0 0 4 1 1 6 ? 1 ? ? 0 ? l c d c k l c d c k c o u n t s o u r c e s e l e c t i o n b i t l c d c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s b i a s c o n t r o l b i t l c d e n a b l e b i t d u t y r a t i o s e l e c t i o n b i t s 2 2 s e l e c t o rs e l e c t o rs e l e c t o r s e l e c t o r s e l e c t o r s e l e c t o r l c d d i s p l a y r a m a d d r e s s 0 0 5 3 1 6 p 1 4 / s e g 3 8 p 3 0 / s e g 1 8 p 1 5 / s e g 3 9 l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t c o m m o n d r i v e r c o m m o n d r i v e r c o m m o n d r i v e r c o m m o n d r i v e r c 1 c 2 v o l t a g e m u l t i p l i e r c o n t r o l b i t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t l e v e l s h i f t s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r s e g m e n t d r i v e r b i a s c o n t r o l l c d o u t p u t e n a b l e b i t v c c
rev.1.01 aug 22, 2003 page 45 of 69 3826 group (a version) v oltage multiplier (3 times) the voltage multiplier performs threefold boosting. this circuit in- puts a reference voltage for boosting from lcd power input pin v l1 . set each bit of the segment output enable register and the lcd mode register in the following order for operating the voltage mul- tiplier. 1. set the segment output enable bits (bits 0 to 5) of the seg- ment output enable register to ?0? or ?1?. 2. set the duty ratio selection bits (bits 0 and 1), the bias con- trol bit (bit 2), the lcd circuit divider division ratio selection bits (bits 5 and 6), and the lcdck count source selection bit (bit 7) of the lcd mode register to ?0? or ?1?. 3. set the lcd output enable bit (bit 6) of the segment output enable register to ?1? (enabled). apply the limit voltage or less to the v l1 pin. 4. set the voltage multiplier control bit (bit 4) of the lcd mode register to ?1? (voltage multiplier enabled). however, be sure to select 1/3 bias for bias control. when voltage is input to the v l1 pin during operating the voltage multiplier, voltage that is twice as large as v l1 occurs at the v l2 pin, and voltage that is three times as large as v l1 occurs at the v l3 pin. notes on voltage multiplier when using the voltage multiplier, apply the limit voltage or less to the v l1 pin, then set the voltage multiplier control bit to ?1? (en- abled). when not using the voltage multiplier, set the lcd output enable bit to ?1?, then apply proper voltage to the lcd power input pins (v l1 ?v l3 ). when the lcd output enable bit is set to ?0? (disabled) (during reset is included), the v l3 pin is connected to v cc inside of this microcomputer. when the voltage exceeding v cc is applied to v l3 , apply v l3 voltage after setting the lcd output enable bit to ?1? (enabled). fig. 47 example of circuit at each bias t able 12 bias control and applied voltage to v l1 ?v l3 bias value 1/3 bias 1/2 bias v oltage value v l3 =v lcd v l2 =2/3 v lcd v l1 =1/3 v lcd v l3 =v lcd v l2 =v l1 =1/2 v lcd note : v lcd is the maximum value of supplied voltage for the lcd panel. bias control and applied voltage to lcd power input pins to the lcd power input pins (v l1 ?v l3 ), apply the voltage shown in table 12 according to the bias value. select a bias value by the bias control bit (bit 2 of the lcd mode register). r4 r5 r 4 = r 5 1 / 2 b i a s r1 r2 r3 v cc v l 3 v l 2 c 2 c 1 v l 1 r1 = r2 = r3 v c c v l 3 v l 2 c 2 c 1 v l 1 v l 3 v l 2 c 2 c 1 v l 1 o pen o pen c o n t r a s t c o n t r o l o pen o pen c o n t r a s t c o n t r o l 1 / 3 b i a s w h e n n o t u s i n g t h e v o l t a g e m u l t i p l i e r 1 / 3 b i a s w h e n u s i n g t h e v o l t a g e m u l t i p l i e r
rev.1.01 aug 22, 2003 page 46 of 69 3826 group (a version) (frequency of count source for lcdck) (divider division ratio for lcd) f(lcdck)= f(lcdck) duty ratio frame frequency= fig. 48 lcd display ram map common pin and duty ratio control the common pins (com 0 ?com 3 ) to be used are determined by duty ratio. select duty ratio by the duty ratio selection bits (bits 0 and 1 of the lcd mode register). after reset, the v cc (v l3 ) voltage is output from the common pins. lcd display ram addresses 0040 16 to 0053 16 are the designated ram for the lcd display. when ?1? are written to these addresses, the correspond- ing segments of the lcd display panel are turned on. lcd drive timing the frequency of internal signal lcdck decided lcd drive timing and the frame frequency can be determined with the following equation: t able 13 duty ratio control and common pins used duty ratio 2 3 4 common pins used notes 1: com 2 and com 3 are open. 2: com 3 is open. bit 1 0 1 1 bit 0 1 0 1 com 0 , com 1 (note 1) com 0 ?com 2 (note 2) com 0 ?com 3 duty ratio selection bits segment signal output pins segment signal output pins are classified into the segment-only pins (seg 0 ?seg 17 ), the segment or output port pins (seg 18 ? seg 25 ), and the segment or i/o port pins (seg 26 ?seg 39 ). segment signals are output according to the bit data of the lcd ram corresponding to the duty ratio. after reset, a v cc (=v l3 ) voltage is output to the segment-only pins and the segment/out- put port pins are the high impedance condition and pulled up to v cc (=v l3 ) voltage. also, the segment/i/o port pins(seg 26 ?seg 39 ) are set to input mode as i/o ports, and v cc (=v l3 ) is applied to them by pull-up resistor. 0 0 4 0 1 6 0 0 4 1 1 6 0 0 4 2 1 6 0 0 4 3 1 6 0 0 4 4 1 6 0 0 4 5 1 6 0 0 4 6 1 6 0 0 4 7 1 6 0 0 4 8 1 6 0 0 4 9 1 6 0 0 4 a 1 6 0 0 4 b 1 6 0 0 4 c 1 6 0 0 4 d 1 6 0 0 4 e 1 6 0 0 4 f 1 6 0 0 5 0 1 6 0 0 5 1 1 6 0 0 5 2 1 6 0 0 5 3 1 6 b i t a d d r e s s s e g 1 s e g 3 s e g 5 s e g 7 s e g 9 s e g 1 1 s e g 1 3 s e g 1 5 s e g 1 7 s e g 1 9 s e g 2 1 s e g 2 3 s e g 2 5 s e g 2 7 s e g 2 9 s e g 3 1 s e g 3 3 s e g 3 5 s e g 3 7 s e g 3 9 76543210 c o m 3 c o m 0 c o m 2 c o m 1 c o m 0 com 3 com 2 c o m 1 seg 0 seg 2 seg 4 seg 6 seg 8 seg 10 seg 12 seg 14 seg 16 seg 18 seg 20 seg 22 seg 24 seg 26 seg 28 seg 30 seg 32 seg 34 seg 36 seg 38
rev.1.01 aug 22, 2003 page 47 of 69 3826 group (a version) fig. 49 lcd drive waveform (1/2 bias) i n t e r n a l s i g n a l l c d c k t i m i n g 1 / 4 d u t y v o l t a g e l e v e l v l 3 v l 2 = v l 1 v s s v l 3 v s s c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 o f fo n o f fo n com 3 c o m 2 c o m 1 c o m 0 com 3 c o m 2 c o m 1 c o m 0 1/3 duty v l3 v l 2 = v l 1 v ss v l 3 v s s o f f o n o no f f o no f f 1 / 2 d u t y com 0 com 1 com 2 s e g 0 c o m 0 c o m 1 seg 0 v l3 v l 2 = v l 1 v s s v l3 v s s o f f o n o f f o n o f f o n o f f o n com 0 com 2 com 1 c o m 0 com 2 com 1 com 0 com 2 c o m 1 c o m 0 c o m 1 c o m 0 c o m 1 c o m 0 c o m 1 c o m 0
rev.1.01 aug 22, 2003 page 48 of 69 3826 group (a version) fig. 50 lcd drive waveform (1/3 bias) i n t e r n a l s i g n a l l c d c k t i m i n g 1 / 4 d u t y volta ge level v l 3 v s s c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 o f fo n o f fo n c o m 3 com 2 c o m 1 c o m 0 c o m 3 c o m 2 c o m 1 com 0 1 / 3 d u t y o f f o n o no f f on o f f 1 / 2 d u t y com 0 com 1 c o m 2 s e g 0 c o m 0 c o m 1 s e g 0 off on off on off on off on v l 3 v l 2 v s s v l 1 v l 3 v l 2 v s s v l1 v l3 v s s v l3 v l 2 v ss v l 1 v l 3 v s s com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 com 1 c o m 0 c o m 1 c o m 0 com 1 c o m 0 c o m 1 com 0
rev.1.01 aug 22, 2003 page 49 of 69 3826 group (a version) w atchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software runaway). the watchdog timer consists of an 8-bit watchdog timer l and a 6- bit watchdog timer h. at reset or writing to the watchdog timer control register (address 0037 16 ), the watchdog timer is set to ?3fff 16 ?. when any data is not written to the watchdog timer con- trol register (address 0037 16 ) after reset, the watchdog timer is stopped. the watchdog timer starts to count down from ?3fff 16 ? by writing to the watchdog timer control register and an internal re- set occurs at an underflow. accordingly, when using the watchdog timer function, write the watchdog timer control register before an underflow. the watchdog timer does not function when writing to the watchdog timer control register has not been done after reset. when not using the watchdog timer, do not write to it. when the watchdog timer control register is read, the following values are read: value of high-order 6-bit counter value of stp instruction disable bit value of count source selection bit. when the stp instruction disable bit is ?0?, the stp instruction is enabled. the stp instruction is disabled when this bit is set to ?1?. if the stp instruction which is disabled is executed, it is processed as an undefined instruction, so that a reset occurs internally. this bit can be set to ?1? but cannot be set to ?0? by program. this bit is ?0? after reset. when the watchdog timer h count source selection bit is ?0?, the detection time is set to 8.19 s at f(x cin ) = 32 khz and 32.768 ms at f(x in ) = 8 mhz. when the watchdog timer h count source selection bit is ?0?, the detection time is set to 32 ms at f(x cin ) = 32 khz and 128 s at f(x in ) = 8 mhz. there is no difference in the detection time be- tween the middle-speed mode and the high-speed mode. fig. 51 block diagram of watchdog timer fig. 52 structure of watchdog timer control register fig. 53 timing of reset output x in data bus x cin ?1? ?0? internal system clock selection bit (note) ?0? ?1? 1/16 watchdog timer h count source selection bit reset circuit undefined instruction reset ?3f 16 ? is set when watchdog timer is written to. internal reset reset reset release time wait ?ff 16 ? is set when watchdog timer is written to. stp instruction stp instruction disable bit watchdog timer h (6) watchdog timer l (8) note: this is the bit 7 of cpu mode register and is used to switch the middle-/high-speed mode and low-speed mode. b 7 b 0 w a t c h d o g t i m e r r e g i s t e r ( w d t c o n : a d d r e s s 0 0 3 7 1 6 ) s t p i n s t r u c t i o n d i s a b l e b i t 0 : s t p i n s t r u c t i o n e n a b l e d 1 : s t p i n s t r u c t i o n d i s a b l e d w a t c h d o g t i m e r h c o u n t s o u r c e s e l e c i o n b i t 0 : w a t c h d o g t i m e r l u n d e r f l o w 1 : f ( x i n ) / 1 6 o r f ( x c i n ) / 1 6 w a t c h d o g t i m e r h ( f o r r e a d - o u t o f h i g h - o r d e r 6 b i t ) ? 3 f f f 1 6 ? i s s e t t o t h e w a t c h d o g t i m e r b y w r i t i n g v a l u e s t o t h i s a d d r e s s . i n t e r n a l r e s e t s i g n a l w a t c h d o g t i m e r d e t e c t i o n a p p r o x . 1 m s ( f ( x i n ) = 8 m h z ) f ( x i n )
rev.1.01 aug 22, 2003 page 50 of 69 3826 group (a version) t out / output function the system clock or timer 2 divided by 2 (t out output) can be output from port p4 3 by setting the t out / output enable bit of the timer 123 mode register and the t out / output control register. set the p4 3 / /t out pin to output mode (set ?1? to bit 3 of port p4 direction register) when outputting t out / . fig. 54 structure of t out / output-related registers t o u t / o u t p u t c o n t r o l b i t 0 : s y s t e m c l o c k o u t p u t 1 : t o u t o u t p u t n o t u s e d ( ? 0 ? a t r e a d i n g ) t out / output contro l reg i ster (ckout : ad dress 002a 16 ) b 7 b 0 ti mer 123 mo d e reg i ster (t123m : a ddress 0029 16 ) t out output act i ve e d ge sw i tc h bi t 0 : start at ?h? output 1 : start at ?l? output t out / output enable bit 0 : t out / output disabled 1 : t out / output enabled time r 2 wr ite co ntrol bit 0 : write data in latch and timer 1 : write data in latch only timer 2 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 3 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 1 count source selection bit 0 : f(x in )/16 (or f(x cin )/16 in low-speed mode) 1 : f(x cin ) not used (?0? at reading) b 7 b 0
rev.1.01 aug 22, 2003 page 51 of 69 3826 group (a version) fig. 55 example of reset circuit reset circuit when the power source voltage is within limits, and main clock x in -x out is stable, or a stabilized clock is input to the x in pin, if the reset pin is held at an ?l? level for 2 s or more, the micro- computer is in an internal reset state. then the reset pin is returned to an ?h? level, reset is released after approximate 8200 cycles of f(x in ), the program in address fffd 16 (high-order byte) fig. 56 reset sequence and address fffc 16 (low-order byte). make sure that the reset in- put voltage is less than 0.2 v cc (min.) for the power source voltage of v cc (min.). *v cc (min.) = minimum value of power supply voltage limits applied to v cc pin v c c r e s e t v c c r e s e t power source voltage detection circuit a d l f f f c fffd a d h , u n d e f i n e d x i n : a p p r o x . 8 2 0 0 c y c l e s n o t e : t h e f r e q u e n c y o f s y s t e m c l o c k i s f ( x i n ) d i v i d e d b y 8 . r e s e t a d d r e s s f r o m v e c t o r t a b l e reset i n t e r n a l r e s e t a d d r e s s d ata sync s y s t e m c l o c k x i n a d h a d l u n d e f i n e dun defined u n d e f i n e d v c c r e s e t p o w e r o n 0 . 2 v c c l e v e l o s c i l l a t i o n s t a b i l i z e d 2 s x in 0v 0v 0v ( n o t e ) n o t e : r e s e t r e l e a s e v o l t a g e v c c = v c c ( m i n . )
rev.1.01 aug 22, 2003 page 52 of 69 3826 group (a version) fig. 57 internal state of microcomputer immediately after reset note: the contents of all other registers and ram are undefined after reset, so they must be initialized by software. ? : undefined register contents address 0001 16 0003 16 0005 16 0007 16 0009 16 000b 16 000d 16 000f 16 0016 16 0017 16 0019 16 001a 16 001b 16 001d 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 0032 16 0033 16 0034 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 (ps) (pc h ) (pc l ) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (1) (2) (3) (4) (5) (6) (7) (8) (9) (35) (36) (37) (38) (39) (40) (41) (42) (43) timer y low-order register port p5 direction register port p6 direction register pull register b timer y high-order register serial i/o1 control register uart control register timer x high-order register timer x low-order register timer x mode register timer y mode register timer 123 mode register serial i/o1 status register port p7 direction register a-d control register segment output enable register lcd mode register pull register a interrupt edge selection register cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 interrupt control register 2 processor status register program counter port p4 direction register port p2 direction register port p3 output control register port p1 direction register port p0 direction register timer 1 register timer 2 register timer 3 register 111000 0 0 100000 0 0 0011 11 1 1 1 0 0 1 0 0 0 0 ? 1 ? ? ?? ?? 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 00 16 00 16 00 16 3f 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 contents of address fffd 16 contents of address fffc 16 d-a control register watchdog timer control register d-a1 conversion register d-a2 conversion register serial i/o2 control register t out / output control register pwm control register watchdog timer (high-order) (44) watchdog timer (low-order) ff 16 01 16 00 16 0 0 0 1 0 0 0 0 3f 16 ff 16 (45) 0015 16 key input control register 00 16 (46) (47) (48) 002e 16 002f 16 0030 16 0031 16 ctcss timer (low-order) ctcss timer (high-order) 06 16 00 16 06 16 06 16 dtmf high group timer dtmf low group timer
rev.1.01 aug 22, 2003 page 53 of 69 3826 group (a version) fig. 58 oscillator circuit fig. 59 external clock input circuit clock generating circuit the 3826 group has two built-in oscillation circuits: main clock x in -x out oscillation circuit and sub-clock x cin -x cout oscillation circuit. an oscillation circuit can be formed by connecting an oscil- lator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the oscillator manufacturer?s recom- mended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an exter- nal feed-back resistor is needed between x cin and x cout since a resistor does not exist between them. to supply a clock signal externally, input it to the x in pin and make the x out pin open. the sub-clock oscillation circuit cannot directly input clocks that are externally generated. accordingly, be sure to cause an external oscillator to oscillate. immediately after poweron, only the x in oscillation circuit starts oscillating, and x cin and x cout pins go to high-impedance state. frequency control (1) middle-speed mode the clock input to the x in pin is divided by 8 and it is used as the system clock . after reset, this mode is selected. (2) high-speed mode the clock input to the x in pin is divided by 2 and it is used as the system clock . (3) low-speed mode ? the clock input to the x cin pin is divided by 2 and it is used as the system clock . ? a low-power consumption operation can be realized by stopping the main clock in this mode. to stop the main clock, set the main clock stop bit of the cpu mode register to ?1?. when the main clock is restarted, after setting the main clock stop bit to ?0?, set enough time for oscillation to stabilize by pro- gram. note: if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the suffi- cient time is required for the sub clock to stabilize, espe- cially immediately after poweron and at returning from stop mode. when switching the mode between middle/high- speed and low-speed, set the frequency in the condition that f(x in ) > 3?f(x cin ). oscillation control (1) stop mode if the stp instruction is executed, the system clock stops at an ?h? level, and main and sub clock oscillators stop. in this time, values set previously to timer 1 latch and timer 2 latch are loaded automatically to timer 1 and timer 2. before the stp instruction, set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits are set to timer 1, high-order 8 bits are set to timer 2). either f(x in ) or f(x cin ) divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits of the timer 123 mode register except bit 4 are set to ?0?. set the timer 1 and timer 2 interrupt enable bits to ?0? before ex- ecuting the stp instruction. oscillation restarts at reset or when an external interrupt is re- ceived, but the system clock is not supplied to the cpu until timer 2 underflows. this allows time for the clock circuit oscillation to stabilize when a ceramic resonator is used. (2) wait mode if the wit instruction is executed, only the system clock stops at an ?h? state. the states of main clock and sub clock are the same as the state before the executing the wit instruction, and oscilla- tion does not stop. since supply of internal clock is started im- mediately after the interrupt is received, the instruction can be ex- ecuted immediately. x c i n c i n c o u t c c i n c c o u t r f r d x c o u t x i n x o u t x i n x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t o p e n v c c v ss c c i n c c o u t r f r d x c i n x c o u t
rev.1.01 aug 22, 2003 page 54 of 69 3826 group (a version) fig. 60 clock generating circuit block diagram wit instru ction stp i nstruct i on s ystem c l oc k s r q stp i nstruct i on s r q m a i n c l oc k stop bi t s r q t i m e r 2 t i m e r 1 1 / 2 1 / 4 x i n x o u t x c o u t x cin i n t e r r u p t r e q u e s t r e s e t t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t l o w - s p e e d m o d e m i d d l e - / h i g h - s p e e d m o d e s y s t e m c l o c k s e l e c t i o n b i t ( n o t e ) middl e-spee d mo d e hi g h -spee d mo d e or low-speed mode n ote: wh en us i ng t h e su b c l oc k f or t h e system c l oc k , set t h e x c sw i tc h bi t to ? 1 ? . m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t ? 1 ? ? 0 ? ? 1 ? ? 0 ? i n t e r r u p t d i s a b l e f l a g i 1 / 2 x c sw i tc h bi t ( n ote ) ? 1 ? ? 0 ?
rev.1.01 aug 22, 2003 page 55 of 69 3826 group (a version) fig. 61 state transitions of system clock n o t e s 1: s w i tc h t h e mo d e a ccor di ng to t h e arrows s h own b etween t h e mo d e bl oc k s. (d o not sw i tc h b etw een t h e mo d e di rect l y w i t h out an arrow. ) 2: the all mo des can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3: when t he stop mode is ended, a delay time can be set by timer 1 and timer 2. 4: time r an d lcd operate in the wait mode. 5: wait until oscillation stabilizes after oscillating the main clock before the switching from the low-speed mode to middle-/hig h-speed mode. 6: the ex ample assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. in di cates the system clock. cm 4 : x c sw i tc h bi t 0: o sc illation stop 1: x cin , x cout cm 5 : main clock (x in ?x out ) stop bit 0: o sc illating 1: stopped cm 6 : main clo ck division ratio selection bit 0: f(x in )/2 (high- s peed mode) 1: f(x in )/8 (middle-speed mode) cm 7 : s ystem clock selection bit 0: x in ?x out selected (midd le-/hi gh-speed mode) 1: x cin ?x cout selected (low-s peed mode ) c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 ) b 7 b 4 r e s e t c m 6 ? 0 ? ? 1 ? c m 6 ? 0 ? ? 1 ? c m 5 ? 0 ? ? 1 ? c m 5 ? 0 ? ? 1 ? ? 0 ? c m 5 c m 6 ? 0 ? ? 1 ? ? 0 ? ? 1 ? c m 5 c m 6 ? 1 ? ? 1 ? ? 0 ? c m 6 ? 0 ? ? 1 ? c m 7 ? 0 ? ? 1 ? c m 7 ? 0 ? ? 1 ? c m 7 = 0 ( 8 m h z s e l e c t e d ) c m 6 = 1 ( m i d d l e - s p e e d ) c m 5 = 0 ( 8 m h z o s c i l l a t i n g ) c m 4 = 0 ( 3 2 k h z s t o p p e d ) m i d d l e - s p e e d m o d e ( f ( ) = 1 m h z ) c m 6 ? 0 ? ? 1 ? c m 4 ? 0 ? ? 1 ? c m 4 ? 0 ? ? 1 ? cm 7 = 0 ( 8 mh z se l ecte d) cm 6 = 0 (hig h-sp eed) cm 5 = 0 (8 mhz oscillating) cm 4 = 0 (3 2 kh z stop ped) h i g h - s p e e d m o d e ( f ( ) = 4 m h z ) cm 7 = 0 ( 8 mh z se l ecte d) cm 6 = 1 (middl e-sp eed) cm 5 = 0 (8 mhz oscillating) cm 4 = 1 (32 khz oscillating) m i d d l e - s p e e d m o d e ( f ( ) = 1 m h z ) cm 7 = 0 ( 8 mh z se l ecte d) cm 6 = 0 (hig h-sp eed) cm 5 = 0 (8 mhz oscillating) cm 4 = 1 (32 khz oscillating) h i g h - s p e e d m o d e ( f ( ) = 4 m h z ) c m 4 c m 6 ? 0 ? ? 1 ? ? 0 ? ? 1 ? c m 4 c m 6 ? 1 ? ? 1 ? ? 0 ? ? 0 ? cm 7 = 1 ( 32 kh z se l ecte d) cm 6 = 1 (middl e-sp eed) cm 5 = 0 (8 mhz oscillating) cm 4 = 1 (32 khz oscillating) l ow-spee d mo d e (f( ) = 16 khz) cm 7 = 1 ( 32 kh z se l ecte d) cm 6 = 0 (hig h-sp eed) cm 5 = 0 (8 mhz oscillating) cm 4 = 1 (32 khz oscillating) l o w- s p e e d m o d e ( f ( ) = 1 6 k h z ) cm 7 = 1 ( 32 kh z se l ecte d) cm 6 = 1 (middl e-sp eed) cm 5 = 1 (8 mhz stop p ed) cm 4 = 1 (32 khz oscillating) l o w- s p e e d m o d e ( f ( ) = 1 6 k h z ) cm 7 = 1 ( 32 kh z se l ecte d) cm 6 = 0 (hig h-sp eed) cm 5 = 1 (8 mhz stop p ed) cm 4 = 1 (32 khz oscillating) l o w- s p e e d m o d e ( f ( ) = 1 6 k h z )
rev.1.01 aug 22, 2003 page 56 of 69 3826 group (a version) notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is ?1?. af- ter a reset, initialize flags (t flag, d flag, etc.) which affect program execution. interrupt when the contents of an interrupt request bits are changed by the program, execute a bbc or bbs instruction after at least one in- struction. this is for preventing executing a bbc or bbs instruction to the contents before change. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to ?1?, then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction before executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. multiplication and division instructions the index mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. the execution of these instructions does not change the contents of the processor status register. ports use instructions such as ldm and sta, etc., to set the port direc- tion registers. the contents of the port direction registers cannot be read. the following cannot be used: ? lda instruction ? the memory operation instruction when the t flag is ?1? ? the bit-test instruction (bbc or bbs, etc.) ? the read-modify-write instruction (calculation instruction such as ror etc., bit manipulation instruction such as clb or seb etc.) ? the addressing mode which uses the value of a direction regis- ter as an index serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit en- able bit, the receive enable bit, and the s rdy output enable bit to ?1?. the txd pin of serial i/o1 retains the level then after transmission is completed. in serial i/o2 selecting an internal clock, the s out2 pin goes to high impedance state after transmission is completed. in serial i/o2 selecting an external clock, the s out2 pin retains the level then after transmission is completed. a-d converter the input to the comparator is combined by internal capacitors. therefore, since conversion accuracy may be worse by losing of an electric charge when the conversion speed is not enough, make sure that f(x in ) is at least 500 khz during an a-d conver- sion. the normal operation of a-d conversion cannot be guaranteed when performing the next operation: ?when writing to cpu mode register during a-d conversion op- eration ?when writing to a-d control register during a-d conversion op- eration ?when executing stp instruction or wit instruction during a-d conversion operation instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the system clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the system clock depends on the main clock division ratio selection bit and the system clock selection bit.
rev.1.01 aug 22, 2003 page 57 of 69 3826 group (a version) notes on use countermeasures against noise (1) shortest wiring length ? wiring for reset pin make the length of wiring which is connected to the reset pin as short as possible. especially, connect a capacitor across the reset pin and the v ss pin with the shortest possible wiring (within 20 mm). reason the width of a pulse input into the reset pin is determined by the timing necessary conditions. if noise having a shorter pulse width than the standard is input to the reset pin, the reset is released before the internal state of the microcomputer is com- pletely initialized. this may cause a program runaway. fig. 63 wiring for clock i/o pins (2) connection of bypass capacitor across v ss line and v cc line in order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 f bypass capacitor across the v ss line and the v cc line as follows: ? connect a bypass capacitor across the v ss pin and the v cc pin at equal length. ? connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. ? use lines with a larger diameter than other signal lines for v ss line and v cc line. ? connect the power source wiring via a bypass capacitor to the v ss pin and the v cc pin. fig. 62 wiring for the reset pin ? wiring for clock input/output pins ? make the length of wiring which is connected to clock i/o pins as short as possible. ? make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. ? separate the v ss pattern only for oscillation from other v ss patterns. reason if noise enters clock i/o pins, clock waveforms may be de- formed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscil- lator, the correct clock will not be input in the microcomputer. fig. 64 bypass capacitor across the v ss line and the v cc line reset reset circuit noise v ss v ss reset circuit v ss reset v ss n.g. o.k. noise x in x out v ss x in x out v ss n.g. o.k. v ss v cc v ss v cc n.g. o.k.
rev.1.01 aug 22, 2003 page 58 of 69 3826 group (a version) rom ordering method 1.mask rom order confirmation form 2.mark specification form 3.data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. ? for the mask rom confirmation and the mark specifications, refer to the ?renesas technology corp.? homepage (http://www.renesas.com/en/rom) (3) oscillator concerns in order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. be careful espe- cially when range of voltage or/and temperature is wide. also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. ? keeping oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the toler- ance of current value flows. reason in the system using a microcomputer, there are signal lines for controlling motors, leds, and thermal heads or others. when a large current flows through those signal lines, strong noise oc- curs because of mutual inductance. ? installing oscillator away from signal lines where potential levels change frequently install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. reason signal lines where potential levels change frequently (such as the cntr pin signal line) may affect other lines at signal rising edge or falling edge. if such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. ? keeping oscillator away from large current signal lines ? installing oscillator away from signal lines where potential levels change frequently fig. 65 wiring for a large current signal line/ w iring of signal lines where potential levels change frequently (4) analog input the analog input pin is connected to the capacitor of a compara- tor. accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of a-d conversion when the analog signal source of high-impedance is connected to an analog input pin. in order to obtain the a-d conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) difference of memory type and size when mask rom and prom version and memory size differ in one group, actual values such as an electrical characteristics, a-d conversion accuracy, and the amount of proof of noise incorrect operation may differ from the ideal values. when these products are used switching, perform system evalua- tion for each product of every after confirming product specification. x i n x o u t v s s m i c r o c o m p u t e r mutual inductance l a r g e c u r r e n t g n d m x i n x o u t v s s c n t r d o n o t c r o s s n.g.
rev.1.01 aug 22, 2003 page 59 of 69 3826 group (a version) electrical characteristics absolute maximum ratings t able 14 absolute maximum ratings recommended operating conditions t able 15 recommended operating conditions (1) (v cc = 1.8 to 5.5 v, ta = ?20 to 85c, unless otherwise noted) power source voltage power source voltage a-d, d-a conversion reference voltage analog power source voltage analog input voltage an 0 ?an 7 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 2.1 v cc v cc v cc v ss v li v ref av ss v ia symbol parameter limits min. v v v v v v v v v v v v v v unit 4.5 4.0 3.0 2.0 3.0 2.0 1.8 1.8 0.15 ? f+1.3 1.3 2.0 av ss 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 1.8 0 t yp. max. power source voltage (note 1) v o v o v o pd t opr t stg ?0.3 to 6.5 v power source voltage input voltage p0 0 ?p0 7 , p1 0 ?p1 7 , p2 0 ?p2 7 , p4 0 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 input voltage p7 0 ?p7 7 input voltage v l1 input voltage v l2 input voltage v l3 input voltage c 1 , c 2 input voltage reset, x in output voltage c 1 , c 2 v cc v i symbol parameter conditions ratings unit all voltages are based on v ss . output transistors are cut off. v i v i v i v i v i v i v o v o v o output voltage p0 0 ?p0 7 , p1 0 ?p1 5 , p3 0 ?p3 7 output voltage p1 6 , p1 7 , p2 0 ?p2 7 , p4 0 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 , p7 1 ?p7 7 output voltage v l3 output voltage v l2 , seg 0 ?seg 17 output voltage x out power dissipation operating temperature storage temperature at output port at segment output ta = 25c ?0.3 to v cc +0.3 ?0.3 to v cc +0.3 ?0.3 to v l2 v l1 to v l3 v l2 to 6.5 ?0.3 to 6.5 ?0.3 to v cc +0.3 ?0.3 to 6.5 ?0.3 to v cc ?0.3 to v l3 ?0.3 to v cc +0.3 ?0.3 to 6.5 ?0.3 to v l3 ?0.3 to v cc +0.3 300 ?20 to 85 ?40 to 125 v v v v v v v v v v v v v v mw c c high-speed mode middle-speed mode low-speed mode at start oscillating (note 2) at using voltage multiplier f(x in ) = 10 mhz f(x in ) = 8 mhz f(x in ) = 6 mhz f(x in ) = 4 mhz f(x in ) = 10 mhz f(x in ) = 8 mhz f(x in ) = 6 mhz notes 1: when using the a-d or d-a converter, refer to ?a-d converter characteristics? or ?d-a converter characteristics?. 2: the oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or t emperature, etc. when power suppl voltage is low and high frequency oscillator is used, an oscillation start will require sufficient conditions. f: this is an oscillator?s oscillation frequency. for example, when oscillation frequency is 8 mhz, substitute ?8?.
rev.1.01 aug 22, 2003 page 60 of 69 3826 group (a version) v v ?h? input voltage p0 0 ?p0 7 , p1 0 ?p1 7 , p4 0 , p4 3 , p4 5 , p4 7 , p5 0 ?p5 3 , p5 6 , p6 1 , p6 4 ?p6 7 , p7 1 ?p7 7 ?h? input voltage p2 0 ?p2 7 , p4 1 , p4 2 , p4 4 , p4 6 , p5 4 , p5 5 , p5 7 , p6 0 , p6 2 , p6 3 , p7 0 reset x in ?l? input voltage p0 0 ?p0 7 , p1 0 ?p1 7 , p4 0 , p4 3 , p4 5 , p4 7 , p5 0 ?p5 3 , p5 6 , p6 1 , p6 4 ?p6 7 , p7 1 ?p7 7 ?l? input voltage p2 0 ?p2 7 , p4 1 , p4 2 , p4 4 , p4 6 , p5 4 , p5 5 , p5 7 , p6 0 , p6 2 , p6 3 , p7 0 reset x in t able 16 recommended operating conditions (2) (v cc = 1.8 to 5.5 v, ta = ?20 to 85c, unless otherwise noted) symbol parameter limits min. unit t yp. max. ?h? input voltage ?h? input voltage v ih v ih v ih v ih v il v il v il v il ?l? input voltage ?l? input voltage 0.7 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0 0 0 0 v cc v cc v cc v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.2 v cc v v v v v v p0 0 ?p0 7 , p1 0 ?p1 7 , p2 0 ?p2 7 , p3 0 ?p3 7 (note 1) p4 1 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 (note 1) p0 0 ?p0 7 , p1 0 ?p1 7 , p2 0 ?p2 7 , p3 0 ?p3 7 (note 1) p4 1 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 (note 1) p4 0 , p7 1 ?p7 7 (note 1) p0 0 ?p0 7 , p1 0 ?p1 7 , p2 0 ?p2 7 , p3 0 ?p3 7 (note 1) p4 1 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 (note 1) p0 0 ?p0 7 , p1 0 ?p1 7 , p2 0 ?p2 7 , p3 0 ?p3 7 (note 1) p4 1 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 (note 1) p4 0 , p7 1 ?p7 7 (note 1) p0 0 ?p0 7 , p1 0 ?p1 5 , p3 0 ?p3 7 (note 2) ?h? peak output current p1 6 , p1 7 , p2 0 ?p2 7 , p4 1 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 (note 2) p0 0 ?p0 7 , p1 0 ?p1 5 , p3 0 ?p3 7 (note 2) ?l? peak output current p1 6 , p1 7 , p2 0 ?p2 7 , p4 1 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 (note 2) p4 0 , p7 1 ?p7 7 (note 2) p0 0 ?p0 7 , p1 0 ?p1 5 , p3 0 ?p3 7 (note 3) p1 6 , p1 7 , p2 0 ?p2 7 , p4 1 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 (note 3) p0 0 ?p0 7 , p1 0 ?p1 5 , p3 0 ?p3 7 (note 3) ?l? average output current p1 6 , p1 7 , p2 0 ?p2 7 , p4 1 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 (note 3) p4 0 , p7 1 ?p7 7 (note 3) ?20 ?20 20 20 80 ?10 ?10 10 10 40 ?1.0 t able 17 recommended operating conditions (3) (v cc = 1.8 to 5.5 v, ta = ?20 to 85c, unless otherwise noted) notes1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current is an average value measured over 100 ms. ?h? total peak output current ?h? total peak output current ?l? total peak output current ?l? total peak output current ?l? total peak output current ?h? total average output current ?h? total average output current ?l? total average output current ?l? total average output current ?l? total average output current i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) i oh(peak) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma ma unit t yp. max. ?h? peak output current ?l? peak output current ?l? peak output current ?h? average output current ?h? average output current ?l? average output current ?l? average output current i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) ?5.0 5.0 10 20 ?0.5 ?2.5 2.5 5.0 ma ma ma ma ma ma ma ma i ol(avg) ma 10
rev.1.01 aug 22, 2003 page 61 of 69 3826 group (a version) t able 18 recommended operating conditions (4) (v cc = 1.8 to 5.5 v, ta = ?20 to 85c, unless otherwise noted) input frequency for timers x and y (duty cycle 50%) f(cntr 0 ) f(cntr 1 ) symbol parameter limits min. mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz khz unit t yp. max. (4.5 v v cc 5.5 v) (4.0 v v cc < 4.5 v) (2.0 v v cc < 4.0 v) (v cc < 2.0 v) high-speed mode (4.5 v v cc 5.5 v) high-speed mode (4.0 v v cc < 4.5 v) high-speed mode (2.0 v v cc < 4.0 v) middle-speed mode (note 3) (3.0 v v cc 5.5 v) middle-speed mode (note 3) (2.0 v v cc 5.5 v) middle-speed mode (note 3) 32.768 5.0 2 ? v cc ?4 v cc 5 ? v cc ?8 10.0 4 ? v cc ?8 2 ? v cc 10.0 8.0 6.0 50 main clock input oscillation frequency (note 1) sub-clock input oscillation frequency (at duty 50 %) (notes 2, 3) f(x in ) f(x cin ) t est conditions notes 1: when using the a-d or d-a converter, refer to ?a-d converter characteristics? or ?d-a converter characteristics?. 2: when using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. 3: the oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or t emperature, etc. when power suppl voltage is low and high frequency oscillator is used, an oscillation start will require sufficient conditions.
rev.1.01 aug 22, 2003 page 62 of 69 3826 group (a version) i il i il i il i ol = 10 ma i ol = 3.0 ma i ol = 2.5 ma v cc = 2.2 v i ol = 5 ma i ol = 1.5 ma i ol = 1.25 ma v cc = 2.2 v v ol i oh = ?1 ma i oh = ?0.25 ma v cc = 2.2 v i oh = ?5 ma i oh = ?1.5 ma i oh = ?1.25 ma v cc = 2.2 v v v cc ?2.0 ?h? output voltage p0 0 ?p0 7 , p1 0 ?p1 5 , p3 0 ?p3 7 symbol parameter limits min. unit 0.5 t yp. max. t est conditions v oh 2.0 0.5 t able 19 electrical characteristics (1) (v cc =4.0 to 5.5 v, ta = ?20 to 85c, unless otherwise noted) i ol = 10 ma i ol = 5 ma v cc = 2.2 v v cc = 2.0 v to 5.0 v v i = v cc v i = v cc v i = v cc v i = v ss pull-ups ?off? v cc = 5 v, v i = v ss pull-ups ?on? v cc = 2.2 v, v i = v ss pull-ups ?on? v i = v ss v i = v ss v cc = 5.0 v, v o = v cc , pullup on output transistors ?off? v cc = 2.2 v,v o = v cc , pullup on output transistors ?off? v o = v cc , pullup off output transistors ?off? v o = v ss , pullup off output transistors ?off? ?h? output voltage p1 6 , p1 7 , p2 0 ?p2 7 , p4 1 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 ?l? output voltage p0 0 ?p0 7 , p1 0 ?p1 5 , p3 0 ?p3 7 ?l? output voltage p1 6 , p1 7 , p2 0 ?p2 7 , p4 1 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 ?l? output voltage p4 0 , p7 1 ?p7 7 hysteresis int 0 ?int 2 , adt, cntr 0, cntr 1, p2 0 ?p2 7 hysteresis s clk , r x d, s in2 hysteresis reset ?h? input current p0 0 ?p0 7 , p1 0 ?p1 7 , p2 0 ?p2 7 , p4 0 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 , p7 0 ?p7 7 ?h? input current reset ?h? input current x in ?l? input current p0 0 ?p0 7 ,p1 0 ?p1 7 , p2 0 ?p2 7 ,p4 1 ?p4 7 , p5 0 ?p5 7 , p6 0 ?p6 7 ?l? input current p4 0 , p7 0 ?p7 7 ?l? input current reset ?l? input current x in output load current p3 0 ?p3 7 v oh v ol v ol v t+ ? v t? v t+ ? v t? v t+ ? v t? i ih i ih i ih i load v cc ?2.0 v cc ?0.5 ?60.0 ?5.0 0.5 0.5 4.0 ?120.0 ?20.0 ?4.0 2.0 0.5 0.5 5.0 5.0 ?5.0 ?240.0 ?40.0 ?5.0 ?5.0 ?240.0 ?40.0 v v v v v v v v v v a a a a a a a a i il v cc ?0.8 v cc ?0.8 v v v 0.8 v 0.8 0.3 v a a a output leak current p3 0 ?p3 7 i leak 5.0 ?5.0 a a ?120.0 ?20.0 ?60.0 ?5.0
rev.1.01 aug 22, 2003 page 63 of 69 3826 group (a version) t able 20 electrical characteristics (2) (v cc = 1.8 to 5.5 v, ta = ?20 to 85c, unless otherwise noted) v 5.5 ? high-speed mode, v cc = 5 v f(x in ) = 10 mhz f(x cin ) = 32.768 khz output transistors ?off? a-d converter in operating ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors ?off? a-d converter in operating ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors ?off? a-d converter stop ? low-speed mode, v cc = 5 v, ta 55c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors ?off? ? low-speed mode, v cc = 5 v, ta = 25c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors ?off? ? low-speed mode, v cc = 3 v, ta 55c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors ?off? ? low-speed mode, v cc = 3 v, ta = 25c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors ?off? all oscillation stopped (in stp state) output transistors ?off? v l1 = 1.8 v symbol parameter limits min. unit t yp. max. ta = 25 c ta = 85 c t est conditions i cc power source current 5.5 v ram ram retention voltage at clock stop mode 1.8 i l1 power source current (v l1 ) (note) note: when the voltage multiplier control bit of the lcd mode register (bit 4 at address 0039 16 ) is ?1?. 4.5 1.2 15 7 9 4.5 9.0 2.4 30 14 18 9.0 1.0 ma ma a a a a a ma 1 1.0 a a 0.1 4.0 10
rev.1.01 aug 22, 2003 page 64 of 69 3826 group (a version) t able 21 a-d converter characteristics (1) (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, ta = ?20 to 85c, f(x in ) = 500 khz to 10 mhz, in middle/high-speed mode unless otherwise noted) 8-bit a-d mode (when conversion mode selection bit (bit 0 of address 0014 16 ) is ?1?) symbol parameter limits min. unit t yp. max. t est conditions ? resolution absolute accuracy (excluding quantization error) v cc = v ref = 2.7 to 5.5 v bits lsb 35 150 8 2 s f(x in ) = 8 mhz conversion time ladder resistor reference power source input current ? t conv r ladder i vref k ? a a t able 22 d-a converter characteristics (v cc = 2.7 to 5.5 v, v cc = v ref , v ss = av ss = 0 v, ta = ?20 to 85c, in middle/high-speed mode unless otherwise noted) symbol parameter limits min. unit t yp. max. t est conditions ? resolution v cc = v ref = 5 v v cc = v ref = 2.7 v 1 bits % % s k ? ma 3 2.5 8 1.0 2.0 note: using one d-a converter, with the value in the d-a conversion register of the other d-a converter being ?00 16 ?, and excluding currents flowing through the a-d resistance ladder. (note) setting time output resistor ? t su r o 4 3.2 12 50 absolute accuracy analog port input current i ia i vref reference power source input current 100 200 5.0 v ref = 5 v 12.5 (note) note: when the internal trigger is used in the middle-speed mode, the max. value of t conv is 14 s.
rev.1.01 aug 22, 2003 page 65 of 69 3826 group (a version) t able 23 timing requirements (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?20 to 85c, unless otherwise noted) 2 100 1000/(4 ? vcc-8) 40 45 40 45 200 1000/(2 ? vcc-4) 85 105 85 105 80 80 800 370 370 220 100 1000 400 400 200 200 note: when bit 6 of address 001a 16 is ?1?. divide this value by four when bit 6 of address 001a 16 is ?0?. reset input ?l? pulse width main clock input cycle time (x in input) main clock input ?h? pulse width main clock input ?l? pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input ?h? pulse width cntr 0 , cntr 1 input ?l? pulse width int 0 to int 3 input ?h? pulse width int 0 to int 3 input ?l? pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input ?h? pulse width (note) serial i/o1 clock input ?l? pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time (note) serial i/o2 clock input ?h? pulse width (note) serial i/o2 clock input ?l? pulse width (note) serial i/o2 input set up time serial i/o2 input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk1 ) t wh(s clk1 ) t wl(s clk1 ) t su(r x d?s clk1 ) t h(s clk1 ?r x d) t c(s clk2 ) t wh(s clk2 ) t wl(s clk2 ) t su(r x d?s clk2 ) t h(s clk2 ?r x d) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit t yp. max. (4.5 v v cc 5.5 v) (4.0 v v cc < 4.5 v) (4.5 v v cc 5.5 v) (4.0 v v cc < 4.5 v) (4.5 v v cc 5.5 v) (4.0 v v cc < 4.5 v) (4.5 v v cc 5.5 v) (4.0 v v cc < 4.5 v) (4.5 v v cc 5.5 v) (4.0 v v cc < 4.5 v) (4.5 v v cc 5.5 v) (4.0 v v cc < 4.5 v)
rev.1.01 aug 22, 2003 page 66 of 69 3826 group (a version) t able 24 timing requirements (2) (v cc = 1.8 to 4.0 v, v ss = 0 v, ta = ?20 to 85c, unless otherwise noted) 2 125 1000/(10 ? vcc-12) 50 70 50 70 1000/v cc 1000/(5 ? vcc-8) t c(cntr) /2?20 t c(cntr) /2?20 reset input ?l? pulse width main clock input cycle time (x in input) main clock input ?h? pulse width main clock input ?l? pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input ?h? pulse width cntr 0 , cntr 1 input ?l? pulse width int 0 to int 3 input ?h? pulse width int 0 to int 3 input ?l? pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input ?h? pulse width (note) serial i/o1 clock input ?l? pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time (note) serial i/o2 clock input ?h? pulse width (note) serial i/o2 clock input ?l? pulse width (note) serial i/o2 input set up time serial i/o2 input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) symbol parameter limits min. s ns ns ns ns ns ns ns ns ns ns unit t yp. max. note: when bit 6 of address 001a 16 is ?1?. divide this value by four when bit 6 of address 001a 16 is ?0?. t wh(int) t wl(int) t c(s clk1 ) t wh(s clk1 ) t wl(s clk1 ) t su(r x d?s clk1 ) t h(s clk1 ?r x d) t c(s clk2 ) t wh(s clk2 ) t wl(s clk2 ) t su(r x d?s clk2 ) t h(s clk2 ?r x d) 230 230 2000 950 950 400 200 2000 950 950 400 200 ns ns ns ns ns ns ns ns ns ns ns ns (2.0 v v cc 4.0 v) (v cc < 2.0 v) (2.0 v v cc 4.0 v) (v cc < 2.0 v) (2.0 v v cc 4.0 v) (v cc < 2.0 v) (2.0 v v cc 4.0 v) (v cc < 2.0 v)
rev.1.01 aug 22, 2003 page 67 of 69 3826 group (a version) t able 25 switching characteristics (1) (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?20 to 85c, unless otherwise noted) note: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is ?0?. serial i/o1 clock output ?h? pulse width serial i/o1 clock output ?l? pulse width serial i/o1 output delay time (note) serial i/o1 output valid time (note) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ?h? pulse width serial i/o2 clock output ?l? pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time 140 30 30 0.2 ? t c (s clk2 ) 40 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns unit t c (s clk1 )/2?30 t c (s clk1 )/2?30 ?30 t yp. max. t wh(s clk1 ) t wl(s clk1 ) t d(s clk1 ?t x d) t v(s clk1 ?t x d) t r(s clk1 ) t f(s clk1 ) t wh(s clk2 ) t wl(s clk2 ) t d(s clk2 ?s out2 ) t v(s clk2 ?s out2 ) t f(s clk2 ) t able 26 switching characteristics (2) (v cc = 1.8 to 4.0 v, v ss = 0 v, ta = ?20 to 85c, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns unit note: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is ?0?. serial i/o1 clock output ?h? pulse width serial i/o1 clock output ?l? pulse width serial i/o1 output delay time (note) serial i/o1 output valid time (note) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output ?h? pulse width serial i/o2 clock output ?l? pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time 350 100 100 0.2 ? t c (s clk2 ) 100 symbol parameter limits min. t c (s clk1 )/2?100 t c (s clk1 )/2?100 ?30 max. t wh(s clk1 ) twl(s clk1 ) t d(s clk1 ?t x d) t v(s clk1 ?t x d) t r(s clk1 ) t f(s clk1 ) t wh(s clk2 ) t wl(s clk2 ) t d(s clk2 ?s out2 ) t v(s clk2 ?s out2 ) t f(s clk2 ) t yp. t c (s clk2 )/2?160 t c (s clk2 )/2?160 0 t c (s clk2 )/2?240 t c (s clk2 )/2?240 0 fig. 66 circuit for measuring output switching characteristics m easurement output p i n 1 0 0 p f c m o s o u t p u t n o t e : w h e n p 7 1 ? p 7 7 , p 4 0 a n d b i t 4 o f t h e u a r t c o n t r o l r e g i s t e r ( a d d r e s s 0 0 1 b 1 6 ) i s ? 1 ? ( n - c h a n n e l o p e n - d r a i n o u t p u t m o d e ) . n - c h a n n e l o p e n - d r a i n o u t p u t ( n o t e ) 1 k ? 1 0 0 p f m easurement output p i n
rev.1.01 aug 22, 2003 page 68 of 69 3826 group (a version) fig. 67 timing diagram i n t 0 ? i n t 2 c n t r 0 , c n t r 1 0.2v cc t w l ( i n t ) 0.8v cc t wh(int) 0.2v cc 0.2v cc 0.8v cc 0.8v cc 0.2v cc t w l ( x i n ) 0.8v cc t wh(x in) t c ( x i n ) x in 0.2v cc 0 . 8 v c c t w(re set) reset t f t r 0 . 2 v c c t wl( cntr) 0 . 8 v c c t wh(c ntr) t c( cntr) t d(s clk1 -t x d) ,t d(s clk2- s out2 ) t v ( s c l k 1 - t x d ) , t v ( s c l k 2 - s o u t 2 ) t c(s clk1 ), t c(s clk2 ) t wl(s clk1 ), t wl(s clk2 ) t wh(s clk1 ), t wh(s clk2 ) th (s clk1- r x d), t h (s clk2- s in 2) t su(r x d - s clk1 ), t su(s in2- s clk2 ) t x d s o u t 2 r x d s i n 2 s c l k 1 s c l k 2
rev.1.01 aug 22, 2003 page 69 of 69 3826 group (a version) package outline lqfp100-p-1414-0.50 w eight(g) 0.63 jedec code eiaj package code lead material cu alloy 100p6q-a plastic 100pin 14 ? 14mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 0.9 m d 14.4 m e 14.4 10 0 0.1 1.0 0.7 0.5 0.3 16.2 16.0 15.8 16.2 16.0 15.8 0.5 14.1 14.0 13.9 14.1 14.0 13.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e h e 1 76 75 51 50 26 25 h d d a f y 100 lp 0.45 0.6 0.25 0.75 0.08 x a3 b x m a 1 a 2 l 1 l detail f lp a3 c m d l 2 b 2 m e e recommended mount pad mmp qfp100-p-1420-0.65 1.58 we ight(g) jedec code eiaj package code lead material alloy 42 100p6s-a plastic 100pin 14 ? 20mm body qfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 i 2 1.3 m d 14.6 m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.65 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 30 31 81 50 80 51 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 x 0.13 b x m mmp
revision history rev. date description page summary 3826 group (a version) data sheet 1.01 aug. 22, 2003 first edition issued ?
keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but ther e is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation p roduct best suited to the customer?s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporat ion or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party?s rights, origin ating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reas ons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracie s or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas te chnology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp oration assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used un der circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor wh en considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com ? 2003. renesas technology corp., all rights reserved. printed in japan.

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